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Wave Pipelining: Theory and CMOS Implementation

  • C. Thomas Gray
  • Wentai Liu
  • Ralph K. CavinIII

Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 248)

Table of contents

  1. Front Matter
    Pages i-xviii
  2. C. Thomas Gray, Wentai Liu, Ralph K. Cavin III
    Pages 1-12
  3. C. Thomas Gray, Wentai Liu, Ralph K. Cavin III
    Pages 13-44
  4. C. Thomas Gray, Wentai Liu, Ralph K. Cavin III
    Pages 45-60
  5. C. Thomas Gray, Wentai Liu, Ralph K. Cavin III
    Pages 61-86
  6. C. Thomas Gray, Wentai Liu, Ralph K. Cavin III
    Pages 87-123
  7. C. Thomas Gray, Wentai Liu, Ralph K. Cavin III
    Pages 125-137
  8. C. Thomas Gray, Wentai Liu, Ralph K. Cavin III
    Pages 139-182
  9. C. Thomas Gray, Wentai Liu, Ralph K. Cavin III
    Pages 183-186
  10. Back Matter
    Pages 187-206

About this book

Introduction

The quest for higher performance digital systems for applications such as gen­ eral purpose computing, signal/image processing, and telecommunications and an increasing cost consciousness have led to a major thrust for high speed VLSI systems implemented in inexpensive and widely available technologies such as CMOS. This monograph, based on the first author's doctoral dissertation, con­ centrates on the technique of wave pipelining as one method toward achieving this goal. The primary focus of this monograph is to provide a coherent pre­ sentation of the theory of wave pipelined operation of digital circuits and to discuss practical design techniques for the realization of wave pipelined circuits in the CMOS technology. Wave pipelining can be applied to a variety of cir­ cuits for increased performance. For example, many architectures that support systolic computation lend themselves to wave pipelined realization. Also, the wave pipeline design methodology emphasizes the role of controlled clock skew in extracting enhanced performance from circuits that are not deeply pipelined. Wave pipelining (also known as maximal rate pipelining) is a timing method­ ology used in digital systems to increase the number of effective pipeline stages without increasing the number of physical registers in the pipeline. Using this technique, new data is applied to the inputs of a combinational logic block be­ fore the outputs due to previous inputs are available thus effectively pipelining the combinational logic and maximizing the utilization of the logic.

Keywords

CMOS algorithms logic model tables

Authors and affiliations

  • C. Thomas Gray
    • 1
  • Wentai Liu
    • 1
  • Ralph K. CavinIII
    • 1
  1. 1.North Carolina State UniversityRaleighUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4615-3206-4
  • Copyright Information Kluwer Academic Publishers 1994
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4613-6407-8
  • Online ISBN 978-1-4615-3206-4
  • Series Print ISSN 0893-3405
  • Buy this book on publisher's site
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