Verification Plans

The Five-Day Verification Strategy for Modern Hardware Verification Languages

  • PeetĀ James

Table of contents

  1. Front Matter
    Pages i-xxii
  2. Peet James
    Pages 1-10
  3. Peet James
    Pages 11-35
  4. Peet James
    Pages 37-54
  5. Peet James
    Pages 55-72
  6. Peet James
    Pages 73-86
  7. Peet James
    Pages 87-100
  8. Peet James
    Pages 101-112
  9. Peet James
    Pages 113-137
  10. Peet James
    Pages 139-145
  11. Back Matter
    Pages 147-230

About this book


Verification isjob one in today's modem design process. Statistics tell us that the verification process takes up a majority of the overall work. Chips that come back dead on arrival scream that verification is at fault for not finding the mistakes. How do we ensure success? After an accomplishment, have you ever had someone ask you, "Are you good or are you just lucky?"? Many design projects depend on blind luck in hopes that the chip will work. Other's, just adamantly rely on their own abilities to bring the chip to success. ill either case, how can we tell the difference between being good or lucky? There must be a better way not to fail. Failure. No one likes to fail. ill his book, "The Logic of Failure", Dietrich Domer argues that failure does not just happen. A series of wayward steps leads to disaster. Often these wayward steps are not really logical, decisive steps, but more like default omissions. Anti-planning if you will, an ad-hoc approach to doing something. To not plan then, is to fail.


Hardware Hardwarebeschreibungssprache Interface Phase chaos complexity development fuzzy hardware verification layers logistics system tables

Authors and affiliations

  • PeetĀ James
    • 1
  1. 1.EVera Consulting CorporationUSA

Bibliographic information

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