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© 2013

Constraining Designs for Synthesis and Timing Analysis

A Practical Guide to Synopsys Design Constraints (SDC)

Benefits

  • Provides a hands-on guide to create constraints for synthesis and timing analysis, using Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints

  • Explains fundamental concepts around SDC constraints and its application in a design

  • Explains SDC command syntax, semantics and options

  • Includes key topics of interest to a synthesis, static timing analysis or place and route engineer

  • Explains which constraints command to use for ease of maintenance and reuse, given several options possible to achieve the same effect on timing

Book

Table of contents

  1. Front Matter
    Pages i-xxvii
  2. Sridhar Gangadharan, Sanjay Churiwala
    Pages 1-8
  3. Sridhar Gangadharan, Sanjay Churiwala
    Pages 9-15
  4. Sridhar Gangadharan, Sanjay Churiwala
    Pages 17-33
  5. Sridhar Gangadharan, Sanjay Churiwala
    Pages 35-46
  6. Sridhar Gangadharan, Sanjay Churiwala
    Pages 47-55
  7. Sridhar Gangadharan, Sanjay Churiwala
    Pages 57-69
  8. Sridhar Gangadharan, Sanjay Churiwala
    Pages 71-80
  9. Sridhar Gangadharan, Sanjay Churiwala
    Pages 81-94
  10. Sridhar Gangadharan, Sanjay Churiwala
    Pages 95-115
  11. Sridhar Gangadharan, Sanjay Churiwala
    Pages 117-130
  12. Sridhar Gangadharan, Sanjay Churiwala
    Pages 131-144
  13. Sridhar Gangadharan, Sanjay Churiwala
    Pages 145-155
  14. Sridhar Gangadharan, Sanjay Churiwala
    Pages 157-166
  15. Sridhar Gangadharan, Sanjay Churiwala
    Pages 167-175
  16. Sridhar Gangadharan, Sanjay Churiwala
    Pages 177-192
  17. Sridhar Gangadharan, Sanjay Churiwala
    Pages 193-207
  18. Sridhar Gangadharan, Sanjay Churiwala, Frederic Revenu
    Pages 209-218
  19. Back Matter
    Pages 219-226

About this book

Introduction

This book serves as a hands-on guide to timing constraints in integrated circuit design.  Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly.  Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing.  Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.

 ·         Provides a hands-on guide to synthesis and timing analysis, using Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints;

·         Includes key topics of interest to a synthesis, static timing analysis or  place and route engineer;

·         Explains which constraints command to use for ease of maintenance and reuse, given several options possible to achieve the same effect on timing;

·         Explains fundamental concepts and provides exact command syntax.

Keywords

ASIC FPGA Integrated Circuit Design Placement and Routing Static Timing Analysis Synopsys Design Constraints (SDC) Timing Analysis Timing Closure Timing Constraints Xilinx Design Constraints

Authors and affiliations

  1. 1.Atrenta, Inc.San JoseUSA
  2. 2.XilinxHyderabadIndia

About the authors

Sanjay Churiwala is an Electronics Engineer from IIT Kharagpur, with two decades of experience in EDA and VLSI. His interest areas include rule checking, synthesis, simulation, STA, Power and Clock Domain Crossings and Synchronization. He currently works at Hyderabad office of Xilinx.

Sridhar Gangadharan  is a Senior Product Engineering Director for Timing Constraints Analysis and SpyGlass  RTL Analysis Products at Atrenta. He has over 20 years of experience in the electronic design automation industry. His interest areas include RTL verification, timing closure, delay calculation and memory compilers. He holds a Bachelors degree in Computer Science and Engineering from Indian Institute of Technology in Delhi. He is based in San Jose, CA.

Bibliographic information

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