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© 2014

Design for Manufacturability

From 1D to 4D for 90–22 nm Technology Nodes

  • Provides design for manufacturability guidelines on layout techniques for the most advanced, 22 nm technology nodes

  • Includes information valuable to layout designers, packaging engineers and quality engineers, working on memories, logic, system-on-chip and system-in-package

  • Offers a highly-accessible, single-source reference to information otherwise available only from disparate sources

  • Helps readers to translate reliability methodology into real design flows

Book
  • 8.2k Downloads

Table of contents

  1. Front Matter
    Pages i-viii
  2. Artur Balasinski
    Pages 1-9
  3. Artur Balasinski
    Pages 11-102
  4. Artur Balasinski
    Pages 103-203
  5. Artur Balasinski
    Pages 205-271
  6. Artur Balasinski
    Pages 273-273
  7. Back Matter
    Pages 275-278

About this book

Introduction

This book explains integrated circuit design for manufacturability (DfM) at the product level (packaging, applications) and applies engineering DfM principles to the latest standards of product development at 22 nm technology nodes.  It is a valuable guide for layout designers, packaging engineers and quality engineers, covering DfM development from 1D to 4D, involving IC design flow setup, best practices, links to manufacturing and product definition, for process technologies down to 22 nm node, and product families including memories, logic, system-on-chip and system-in-package.

·         Provides design for manufacturability guidelines on layout techniques for the most advanced, 22 nm  technology nodes;

·         Includes information valuable to layout designers, packaging engineers and quality engineers, working on memories, logic, system-on-chip and system-in-package; 

·         Offers a highly-accessible, single-source reference to information otherwise available only from disparate sources;

·         Helps readers to translate reliability methodology into real design flows.

Keywords

22nm technology node DFM 3D Design for manufacturability DFM Design for manufacturability Integrated Circuits Memory Design for manufacturability System in Package System on Chip X-fab manufacturability

Authors and affiliations

  1. 1.Cypress SemiconductorSan DiegoUSA

About the authors

Artur Balasinski is a Technology Design Integration Manager for Cypress Semiconductor in San Jose, California.

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