Cache and Interconnect Architectures in Multiprocessors

  • Michel Dubois
  • Shreekant S. Thakkar

Table of contents

  1. Front Matter
    Pages i-xiii
  2. TLB Consistency and Virtual Caches

    1. Patricia J. Teller
      Pages 1-14
    2. Michel Cekleov, Michel Dubois, Jin-Chin Wang, Fayé A. Briggs
      Pages 15-35
  3. Simulation and Performance Studies — Cache Coherence

  4. Cache Coherence Protocols

    1. Erik Hagersten, Seif Haridi, David H. D. Warren
      Pages 165-188
  5. Interconnect Architectures

    1. Andy Hopper, Alan Jones, Dimitris Lioupis
      Pages 209-222
    2. Vason P. Srini
      Pages 223-243
    3. Dimitris Lioupis, Nikos Kanellopoulos
      Pages 245-257
  6. Software Cache Coherence Schemes

    1. Hoichi Cheong, Alexander V. Veidenbaum
      Pages 259-276
  7. Back Matter
    Pages 277-277

About this book


Cache And Interconnect Architectures In Multiprocessors Eilat, Israel May 25-261989 Michel Dubois UniversityofSouthernCalifornia Shreekant S. Thakkar SequentComputerSystems The aim of the workshop was to bring together researchers working on cache coherence protocols for shared-memory multiprocessors with various interconnect architectures. Shared-memory multiprocessors have become viable systems for many applications. Bus­ based shared-memory systems (Eg. Sequent's Symmetry, Encore's Multimax) are currently limited to 32 processors. The fIrst goal of the workshop was to learn about the performance ofapplications on current cache-based systems. The second goal was to learn about new network architectures and protocols for future scalable systems. These protocols and interconnects would allow shared-memory architectures to scale beyond current imitations. The workshop had 20 speakers who talked about their current research. The discussions were lively and cordial enough to keep the participants away from the wonderful sand and sun for two days. The participants got to know each other well and were able to share their thoughts in an informal manner. The workshop was organized into several sessions. The summary of each session is described below. This book presents revisions of some of the papers presented at the workshop.


Fusion Microsoft Access architecture computer evaluation form interface network parallel programming patterns performance performance evaluation processor software validation

Editors and affiliations

  • Michel Dubois
    • 1
  • Shreekant S. Thakkar
    • 2
  1. 1.University of Southern CaliforniaUSA
  2. 2.Sequent Computer SystemsUSA

Bibliographic information

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