Hierarchical Modeling for VLSI Circuit Testing

  • Debashis Bhattacharya
  • John P. Hayes

Table of contents

  1. Front Matter
    Pages i-xi
  2. Debashis Bhattacharya, John P. Hayes
    Pages 1-30
  3. Debashis Bhattacharya, John P. Hayes
    Pages 31-60
  4. Debashis Bhattacharya, John P. Hayes
    Pages 61-96
  5. Debashis Bhattacharya, John P. Hayes
    Pages 97-127
  6. Debashis Bhattacharya, John P. Hayes
    Pages 129-132
  7. Back Matter
    Pages 133-159

About this book


Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob­ lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.


Multiplexer Signal VLSI algorithms data structures design development integrated circuit interconnect logic model modeling simulation stability technology

Authors and affiliations

  • Debashis Bhattacharya
    • 1
  • John P. Hayes
    • 2
  1. 1.Yale UniversityUSA
  2. 2.The University of MichiganUSA

Bibliographic information

  • DOI
  • Copyright Information Springer-Verlag US 1990
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4612-8819-0
  • Online ISBN 978-1-4613-1527-8
  • Series Print ISSN 0893-3405
  • Buy this book on publisher's site
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