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Quick-Turnaround ASIC Design in VHDL

Core-Based Behavioral Synthesis

  • Mohamed S. Ben Romdhane
  • Vijay K. Madisetti
  • John W. Hines

Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 367)

Table of contents

  1. Front Matter
    Pages i-xviii
  2. Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines
    Pages 1-10
  3. Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines
    Pages 11-35
  4. Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines
    Pages 37-47
  5. Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines
    Pages 49-85
  6. Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines
    Pages 87-122
  7. Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines
    Pages 123-133
  8. Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines
    Pages 135-141
  9. Back Matter
    Pages 143-180

About this book

Introduction

From the Foreword.....
Modern digital signal processing applications provide a large challenge to the system designer. Algorithms are becoming increasingly complex, and yet they must be realized with tight performance constraints. Nevertheless, these DSP algorithms are often built from many constituent canonical subtasks (e.g., IIR and FIR filters, FFTs) that can be reused in other subtasks. Design is then a problem of composing these core entities into a cohesive whole to provide both the intended functionality and the required performance.
In order to organize the design process, there have been two major approaches. The top-down approach starts with an abstract, concise, functional description which can be quickly generated. On the other hand, the bottom-up approach starts from a detailed low-level design where performance can be directly assessed, but where the requisite design and interface detail take a long time to generate. In this book, the authors show a way to effectively resolve this tension by retaining the high-level conciseness of VHDL while parameterizing it to get good fit to specific applications through reuse of core library components. Since they build on a pre-designed set of core elements, accurate area, speed and power estimates can be percolated to high- level design routines which explore the design space. Results are impressive, and the cost model provided will prove to be very useful. Overall, the authors have provided an up-to-date approach, doing a good job at getting performance out of high-level design.
The methodology provided makes good use of extant design tools, and is realistic in terms of the industrial design process. The approach is interesting in its own right, but is also of direct utility, and it will give the existing DSP CAD tools a highly competitive alternative. The techniques described have been developed within ARPAs RASSP (Rapid Prototyping of Application Specific Signal Processors) project, and should be of great interest there, as well as to many industrial designers.
Professor Jonathan Allen, Massachusetts Institute of Technology

Keywords

ASIC ASSP Signal VHDL algorithm algorithms computer-aided design (CAD) design process digital signal processing digital signal processor fast Fourier transform (FFT) integrated circuit model signal processing software

Editors and affiliations

  • Mohamed S. Ben Romdhane
    • 1
  • Vijay K. Madisetti
    • 2
  • John W. Hines
    • 3
  1. 1.Rockwell International CorporationUSA
  2. 2.Georgia Institute of Technology & VP TechnologiesUSA
  3. 3.US Air Force Wright LaboratoriesUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4613-1411-0
  • Copyright Information Springer-Verlag US 1996
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4612-8612-7
  • Online ISBN 978-1-4613-1411-0
  • Series Print ISSN 0893-3405
  • Buy this book on publisher's site
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