About this book
Low Power Networks-on-Chip
In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issues
still represent one of the limiting factors in integrating multi- and many-cores
on a single chip.
This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.
•Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures;
•Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect;
•Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings.
Embedded Systems High Speed Interconnect Low Power Design Network on Chip On-Chip Communication Architectures System-on-Chip