© 2009

Designing Reliable and Efficient Networks on Chips

  • Authors
  • First book that presents in depth the state-of-the-art algorithms and optimization models for performing system-level design of NoCs

  • Presents an integrated flow to design interconnect architectures that can lead to faster time-to-market and design closure

  • Shows evolution of design methods from complex crossbar based buses to NoCs

  • Presents static and run-time methods for achieving reliable operation of the NoC and the entire system


Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 34)

Table of contents

  1. Front Matter
    Pages i-x
  2. Introduction

    1. Srinivasan Murali
      Pages 1-12
  3. NoC Design Methods

    1. Front Matter
      Pages 12-12
    2. Srinivasan Murali
      Pages 15-37
    3. Srinivasan Murali
      Pages 39-42
    4. Srinivasan Murali
      Pages 43-56
    5. Srinivasan Murali
      Pages 57-75
    6. Srinivasan Murali
      Pages 77-93
    7. Srinivasan Murali
      Pages 95-113
  4. NoC Reliability Mechanisms

    1. Front Matter
      Pages 115-115
    2. Srinivasan Murali
      Pages 117-139
    3. Srinivasan Murali
      Pages 141-152
    4. Srinivasan Murali
      Pages 153-167
    5. Srinivasan Murali
      Pages 169-186
    6. Srinivasan Murali
      Pages 187-189
  5. Back Matter
    Pages 191-198

About this book


Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.


Design Networks on Chips Reliability Systems on Chips Topology integrated circuit metal-oxide-semiconductor transistor

About the authors

Dr. Srinivasan Murali is a co-founder and CTO of iNoCs and a research scientist at the Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland. He received the MS and PhD degrees in Electrical Engineering from Stanford University in 2007. His research interests include interconnect design for Systems on Chips, with particular emphasis on developing CAD tools and design methods for Networks on Chips. His interests also include thermal modeling and reliability of multi-core systems. He has been actively involved in several conferences (such as DATE, CODES-ISSS, NoC symposium, VLSI-SoC) as a program committee member/session chair and is a reviewer for many leading conferences and journals. He is a recipient of the EDAA outstanding dissertation award for 2007 for his work on interconnect architecture design.  He received a best paper award at the DATE 2005 conference and a best paper nomination at the ICCAD 2006 conference. 

One of his papers has also been selected as one of "The Most Influential Papers of 10 Years DATE". He has over 30 publications in leading conferences and journals in this field.

Bibliographic information

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