About this book
Timing Optimization Through Clock Skew Scheduling focuses on optimizing the timing of large scale, high performance, digital synchronous systems. A particular emphasis is placed on algorithms for non-zero clock skew scheduling to improve the performance and reliability of VLSI circuits.
This research monograph answers the need for a broad introduction to state-of-the-art clock skew scheduling algorithms from a circuit, graph, and mathematical optimization background. A detailed description of clock skew scheduling application on edge-triggered and level-sensitive circuits, synchronized with single and multi-phase clocking schemes, and formulated as linear programming (LP) and quadratic programming (QP) formulations are provided along with an analysis of optimal computer solution techniques. Theoretical limits of improvement in clock frequency through clock skew scheduling are highlighted. Hints and a preliminary implementation of a parallel skew scheduling application are also included.
Timing Optimization Through Clock Skew Scheduling contains sufficient detail for the advanced CAD algorithm developer, researcher and graduate student. Furthermore, with the material provided on timing properties and optimization, those readers with less background can also benefit from this book.
Editors and affiliations
- Book Title Timing Optimization Through Clock Skew Scheduling
- DOI https://doi.org/10.1007/978-0-387-71056-3
- Copyright Information Springer US 2009
- Publisher Name Springer, Boston, MA
- eBook Packages Engineering Engineering (R0)
- Hardcover ISBN 978-0-387-71055-6
- Softcover ISBN 978-1-4419-4377-4
- eBook ISBN 978-0-387-71056-3
- Edition Number 1
- Number of Pages XVI, 266
- Number of Illustrations 0 b/w illustrations, 0 illustrations in colour
Circuits and Systems
Computer-Aided Engineering (CAD, CAE) and Design
Electronics and Microelectronics, Instrumentation
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