Table of contents
About this book
Functional verification has become an important aspect of the chip design process. Significant resources, both in industry and academia, are devoted to the design complexity and verification endeavors.
SAT-Based Scalable Formal Verification Solutions discusses in detail several of the latest and interesting scalable SAT-based techniques including: Hybrid SAT Solver, Customized Bounded/Unbounded Model Checking, Distributed Model Checking, Proofs and Proof-based Abstraction Methods, Verification of Embedded Memory System & Multi-clock Systems, and Synthesis for Verification Paradigm. These techniques have been designed and implemented in a verification platform Verisol (formally called DiVer) and have been used successfully in industry. This book provides algorithmic details and engineering insights into devising scalable approaches for an effective realization. It also includes the authors’ practical experiences and recommendations in verifying the large industry designs using VeriSol.
The book is primarily written for researchers, scientists, and verification engineers who would like to gain an in-depth understanding of scalable SAT-based verification techniques. The book will also be of interest for CAD tool developers who would like to incorporate various SAT-based advanced techniques in their products.
- Book Title SAT-Based Scalable Formal Verification Solutions
- Series Title Series on Integrated Circuits and Systems
- DOI https://doi.org/10.1007/978-0-387-69167-1
- Copyright Information Springer-Verlag US 2007
- Publisher Name Springer, Boston, MA
- eBook Packages Computer Science Computer Science (R0)
- Hardcover ISBN 978-0-387-69166-4
- Softcover ISBN 978-1-4419-4341-5
- eBook ISBN 978-0-387-69167-1
- Series ISSN 1558-9412
- Edition Number 1
- Number of Pages XXX, 330
- Number of Illustrations 118 b/w illustrations, 0 illustrations in colour
Computer-Aided Engineering (CAD, CAE) and Design
Circuits and Systems
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