Table of contents

  1. Front Matter
  2. M. Mehring, H. Sixl
    Pages 11-28
  3. V. Cantoni, M. Ferretti
    Pages 58-74
  4. G. Scarpetta, G. Simoncelli
    Pages 87-119
  5. Albrecht A. C. von Müller
    Pages 150-157
  6. J. D. Becker
    Pages 158-165
  7. U. Rückert, K. Goser
    Pages 166-184
  8. E. R. Caianiello, M. Marinaro
    Pages 198-205
  9. A. Bertoni, M. Goldwurm, G. Mauri, N. Sabadini
    Pages 206-226

About these proceedings


WOPPLOT 86 - Workshop on Parallel Processing: Logic, Organization and Technology - gathered together experts from various fields for a broad overview of current trends in parallel processing. There are contributions from logic (e.g., the connection between time and logic, or non-monotonic reasoning); from organizational structure theory (of great importance for pyramid architecture) and structure representation; from intrinsic parallelism and problem classification; from developments in future technologies (3-D Silicon technology, molecular electronics); and from various applications (pattern storage in adaptive memories, simulation of physical systems). The proceedings show clearly that progress in parallel processing is an interdisciplinary goal; they present a cross section of the state of the art as well as of future trends. Furthermore, some contributions (in particular, those from logic and organization) deserve a broader interest also outside the field of parallel processing.


algorithms image processing neural network parallel computing programming

Bibliographic information

  • Book Title WOPPLOT 86 Parallel Processing: Logic, Organization, and Technology
  • Book Subtitle Proceedings of a Workshop Neubiberg, Federal Republic of Germany, July 2–4, 1986
  • Editors Jörg D. Becker
    Ignaz Eisele
  • Series Title Lecture Notes in Computer Science
  • Series Abbreviated Title Lect Notes Comput Sci
  • DOI
  • Copyright Information Springer-Verlag Berlin Heidelberg 1987
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Springer Book Archive
  • Softcover ISBN 978-3-540-18022-7
  • eBook ISBN 978-3-540-47709-9
  • Series ISSN 0302-9743
  • Series E-ISSN 1611-3349
  • Edition Number 1
  • Number of Pages VIII, 228
  • Number of Illustrations 0 b/w illustrations, 0 illustrations in colour
  • Topics Processor Architectures
  • Buy this book on publisher's site
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