Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings

  • Johan Vounckx
  • Nadine Azemard
  • Philippe Maurine
Conference proceedings PATMOS 2006

Part of the Lecture Notes in Computer Science book series (LNCS, volume 4148)

Table of contents

  1. Front Matter
  2. Session 1 – High-Level Design

    1. Daniele Paolo Scarpazza, Praveen Raghavan, David Novo, Francky Catthoor, Diederik Verkest
      Pages 12-23
    2. Vasily G. Moshnyaga, Hoa Vo, Glenn Reinman, Miodrag Potkonjak
      Pages 24-35
  3. Session 2 – Power Estimation / Modeling

    1. Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri
      Pages 36-46
    2. Xiao Yan Yu, Robert Montoye, Kevin Nowka, Bart Zeydel, Vojin Oklobdzija
      Pages 47-55
    3. Jose L. Rosselló, Carol de Benito, Sebastià Bota, Jaume Segura
      Pages 66-74
  4. Session 3 – Memory and Register Files

    1. A. G. Silva-Filho, F. R. Cordeiro, R. E. Sant’Anna, M. E. Lima
      Pages 75-83
    2. Hanene Ben Fradj, Cécile Belleudy, Michel Auguin
      Pages 84-94
    3. Ka-Ming Keung, Akhilesh Tyagi
      Pages 95-106
    4. David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest et al.
      Pages 107-116
  5. Session 4 – Low-Power Digital Circuits

  6. Session 5 – Busses and Interconnects

  7. Session 6 – Low Power Techniques

  8. Session 7 – Applications and SoC Design

    1. Tiago Dias, Nuno Roma, Leonel Sousa
      Pages 247-255
    2. Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez
      Pages 267-279
    3. Julien Mercier, Christian Dufaza, Mathieu Lisart
      Pages 280-291
    4. Jong-pil Son, Kyu-young Kim, Ji-yong Jeong, Yogendera Kumar, Soo-won Kim
      Pages 292-300
  9. Session 8 – Modeling

    1. Daniel Lima Ferrão, Ricardo Reis, José Luís Güntzel
      Pages 301-310
    2. Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
      Pages 311-318
    3. Christophe Alexandre, Marek Sroka, Hugo Clément, Christian Masson
      Pages 319-328
    4. Mini Nanua, David Blaauw
      Pages 329-339
    5. Ajoy K. Palit, Kishore K. Duganapalli, Walter Anheier
      Pages 340-349
  10. Session 9 – Digital Circuits

    1. Ji-Yong Jeong, Gil-Su Kim, Jong-Pil Son, Woo-Jin Rim, Soo-Won Kim
      Pages 350-359
    2. Christophe Giacomotto, Nikola Nedovic, Vojin G. Oklobdzija
      Pages 360-369
    3. Hai Lin, Yu Wang, Rong Luo, Huazhong Yang, Hui Wang
      Pages 370-381
    4. Jianping Hu, Hong Li, Yangbo Wu
      Pages 382-392
    5. Masayuki Kitamura, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Hiromi Notani, Akira Tada et al.
      Pages 393-402
  11. Session 10 – Reconfigurable and Programmable Devices

    1. Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis
      Pages 403-414
    2. David Elléouet, Yannig Savary, Nathalie Julien
      Pages 415-424
  12. Poster 1

    1. Raúl Jiménez, Pilar Parra, Javier Castro, Manuel Sánchez, Antonio Acosta
      Pages 439-449
    2. Benjamin Nicolle, William Tatinian, Jean Oudinot, Gilles Jacquemod
      Pages 450-457
    3. Régis Roubadia, Sami Ajram, Guy Cathébras
      Pages 458-467
    4. V. Migairou, R. Wilson, S. Engels, N. Azemard, P. Maurine
      Pages 468-476
    5. Saihua Lin, Hongli Gao, Huazhong Yang
      Pages 486-495

About these proceedings


Welcome to the proceedings of PATMOS 2006, the 16th in a series of international workshops. PATMOS 2006 was organized by LIRMM with CAS technical - sponsorship and CEDA sponsorship. Over the years, the PATMOS workshop has evolved into an important European event, where researchers from both industry and academia discuss and investigate the emerging challenges in future and contemporary applications, design methodologies, and tools required for the development of upcoming generations of integrated circuits and systems. The technical program of PATMOS 2006 contained state-of-the-art technical contributions, three invited talks, a special session on hearing-aid design, and an embedded tutorial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert reviewers, selected the 64 papers presented at PATMOS. The papers were organized into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript.


DOM calculus circuit design configuration electromagnetic compatibility field-effect transistor integrated circuit integrated circuits low power desing metal oxide semiconductur field-effect transistor optimization performance evaluation power consumption processor architecture systems design

Editors and affiliations

  • Johan Vounckx
    • 1
  • Nadine Azemard
    • 2
  • Philippe Maurine
    • 3
  1. 1.IMECHeverleeBelgium
  2. 2.LIRMMUMR CNRS/Université de Montpellier II, (C5506)MontpellierFrance
  3. 3.University of Montpellier / LIRMM, IIMontpellierFrance

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