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High Performance Embedded Architectures and Compilers

First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005. Proceedings

  • Tom Conte
  • Nacho Navarro
  • Wen-mei W. Hwu
  • Mateo Valero
  • Theo Ungerer
Conference proceedings HiPEAC 2005

Part of the Lecture Notes in Computer Science book series (LNCS, volume 3793)

Table of contents

  1. Front Matter
  2. Invited Program

    1. Front Matter
      Pages 1-1
    2. Hyunseok Lee, Yuan Lin, Yoav Harel, Mark Woh, Scott Mahlke, Trevor Mudge et al.
      Pages 6-26
  3. I Analysis and Evaluation Techniques

    1. Front Matter
      Pages 27-27
    2. Grigori Fursin, Albert Cohen, Michael O’Boyle, Olivier Temam
      Pages 29-46
    3. Michael Van Biesbrouck, Lieven Eeckhout, Brad Calder
      Pages 47-67
    4. Jia Yu, Jun Yang, Shaojie Chen, Yan Luo, Laxmi Bhuyan
      Pages 68-83
  4. II Novel Memory and Interconnect Architectures

    1. Front Matter
      Pages 85-85
    2. David Moloney, Dermot Geraghty, Colm McSweeney, Ciaran McElroy
      Pages 116-129
    3. Gansha Wu, Xin Zhou, Guei-Yuan Lueh, Jesse Z Fang, Peng Guo, Jinzhan Peng et al.
      Pages 130-149
  5. III Security Architecture

    1. Front Matter
      Pages 151-151
    2. Weidong Shi, Chenghuai Lu, Hsien-Hsin S. Lee
      Pages 153-168
    3. Abdulhadi Shoufan, Sorin A. Huss, Murtuza Cutleriwala
      Pages 169-183
    4. Mahadevan Gomathisankaran, Akhilesh Tyagi
      Pages 184-199
  6. IV Novel Compiler and Runtime Techniques

    1. Front Matter
      Pages 201-201
    2. Jinpyo Kim, Sreekumar V. Kodakara, Wei-Chung Hsu, David J. Lilja, Pen-Chung Yew
      Pages 203-217
    3. Sebastian Pop, Albert Cohen, Georges-André Silber
      Pages 218-232
    4. Dries Buytaert, Kris Venstermans, Lieven Eeckhout, Koen De Bosschere
      Pages 233-248
  7. V DomainSpecificArchitectures

    1. Front Matter
      Pages 249-249
    2. Bengu Li, Ganesh Venkatesh, Brad Calder, Rajiv Gupta
      Pages 251-265
    3. P. J. García, J. Flich, J. Duato, I. Johnson, F. J. Quiles, F. Naven
      Pages 266-285
    4. Victor Moya, Carlos González, Jordi Roca, Agustín Fernández, Roger Espasa
      Pages 286-301
    5. Hyun-Gyu Kim, Hyeong-Cheol Oh
      Pages 302-316
  8. Back Matter

About these proceedings

Introduction

As Chairmen of HiPEAC 2005, we have the pleasure of welcoming you to the proceedings of the ?rst international conference promoted by the HiPEAC N- work of Excellence. During the last year, HiPEAC has been building its clusters of researchers in computer architecture and advanced compiler techniques for embedded and high-performance computers. Recently, the Summer School has been the seed for a fruitful collaboration of renowned international faculty and young researchers from 23 countries with fresh new ideas. Now, the conference promises to be among the premier forums for discussion and debate on these research topics. Theprestigeofasymposiumismainlydeterminedbythequalityofitstech- cal program. This ?rst programlived up to our high expectations, thanks to the largenumber of strong submissions. The ProgramCommittee received a total of 84 submissions; only 17 were selected for presentation as full-length papers and another one as an invited paper. Each paper was rigorously reviewed by three ProgramCommittee members and at least one external referee. Many reviewers spent a great amount of e?ort to provide detailed feedback. In many cases, such feedback along with constructive shepherding resulted in dramatic improvement in the quality of accepted papers. The names of the Program Committee m- bers and the referees are listed in the proceedings. The net result of this team e?ort is that the symposium proceedings include outstanding contributions by authors from nine countries in three continents. In addition to paper presentations, this ?rst HiPEAC conference featured two keynotes delivered by prominent researchers from industry and academia.

Keywords

Compiler compiler techniques computer architecture dynamic compilation embedded systems high-performance architecture memory system organization network computing network processors parallel architectures performance evaluation processor architectures reconfigurable architectures secured computing security processors

Editors and affiliations

  • Tom Conte
    • 1
  • Nacho Navarro
    • 2
  • Wen-mei W. Hwu
    • 3
  • Mateo Valero
    • 4
  • Theo Ungerer
    • 5
  1. 1.NC State UniversityUSA
  2. 2.UPCSpain
  3. 3.Center for Reliable and High-Performance Computing and Department of Electrical and Computer EngineeringUniversity of Illinois at Urbana-Champaign 
  4. 4.Barcelona Supercomputing Center-CNSSpain
  5. 5.Department of Computer ScienceUniversity of AugsburgAugsburgGermany

Bibliographic information

  • DOI https://doi.org/10.1007/11587514
  • Copyright Information Springer-Verlag Berlin Heidelberg 2005
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Computer Science
  • Print ISBN 978-3-540-30317-6
  • Online ISBN 978-3-540-32272-6
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349
  • Buy this book on publisher's site
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