© 2005

Power-Aware Computer Systems

4th International Workshop, PACS 2004, Portland, OR, USA, December 5, 2004, Revised Selected Papers

  • Babak Falsafi
  • T. N. VijayKumar
Conference proceedings PACS 2004

Part of the Lecture Notes in Computer Science book series (LNCS, volume 3471)

Table of contents

  1. Front Matter
  2. Microarchitecture- and Circuit-Level Techniques

    1. Miquel Pericàs, Ruben Gonzalez, Adrian Cristal, Alex Veidenbaum, Mateo Valero
      Pages 1-14
    2. Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin
      Pages 15-29
    3. Sumeet Kumar, Prateek Pujara, Aneesh Aggarwal
      Pages 30-45
    4. Eren Kursun, Glenn Reinman, Suleyman Sair, Anahita Shayesteh, Tim Sherwood
      Pages 46-60
  3. Power-Aware Memory and Interconnect Systems

    1. H. Huang, K. G. Shin, C. Lefurgy, K. Rajamani, T. Keller, E. Hensbergen et al.
      Pages 61-77
    2. Yao Guo, Saurabh Chheda, Israel Koren, C. Mani Krishna, Csaba Andras Moritz
      Pages 78-94
    3. Kartik Mohanram, Scott Rixner
      Pages 107-119
  4. Frequency-/Voltage-Scaling Techniques

    1. Masaaki Kondo, Hiroshi Nakamura
      Pages 120-134
    2. Chung-Hsing Hsu, Wu-Chun Feng
      Pages 135-149
    3. Aqeel Mahesri, Vibhore Vardhan
      Pages 165-180
  5. Erratum

    1. Editorial Board
      Pages E1-E1
  6. Back Matter

About these proceedings


Welcome to the proceedings of the Power-Aware Computer Systems (PACS 2004) workshop held in conjunction with the 37th Annual International Sym- sium on Microarchitecture (MICRO-37). The continued increase of power and energy dissipation in computer systems has resulted in higher cost, lower re- ability, and reduced battery life in portable systems. Consequently, power and energy have become ?rst-class constraints at all layers of modern computer s- tems. PACS 2004 is the fourth workshop in its series to explore techniques to reduce power and energy at all levels of computer systems and brings together academic and industry researchers. The papers in these proceedings span a wide spectrum of areas in pow- aware systems. We have grouped the papers into the following categories: (1) microarchitecture- and circuit-level techniques, (2) power-aware memory and interconnect systems, and (3) frequency- and voltage-scaling techniques. The ?rst paper in the microarchitecture group proposes banking and wri- back ?ltering to reduce register ?le power. The second paper in this group - timizes both delay and power of the issue queue by packing two instructions in each issue queue entry and by memorizing upper-order bits of the wake-up tag. The third paper proposes bit slicing the datapath to exploit narrow width operations, and the last paper proposes to migrate application threads from one core to another in a multi-core chip to address thermal problems.


Computer Embedded System architecture circuit design embedded systems energy dissipation hardware design logic low power consumption microprocessor performance analysis power optimization power-aware computer systems power-aware computing system on chip (SoC)

Editors and affiliations

  • Babak Falsafi
    • 1
  • T. N. VijayKumar
    • 2
  1. 1.Electrical and Computer Engineering, Computer ScienceCarnegie Mellon UniversityPittsburghUSA
  2. 2.ECEPurdue UniversityUSA

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