Design of Systems on a Chip: Design and Test

  • Ricardo Reis
  • Marcelo Lubaszewski
  • Jochen A.G. Jess

Table of contents

  1. Front Matter
    Pages I-X
  2. Marcelo Lubaszewski, Ricardo Reis, Jochen A.G. Jess
    Pages 1-7
  3. J. Malcolm Wilkinson
    Pages 9-25
  4. François Anceau
    Pages 65-82
  5. Ricardo Reis, Josè Luìs Güntzel, Marcelo Johann
    Pages 83-102
  6. Reinaldo A. Bergamaschi
    Pages 103-131
  7. A. Jerraya, J.M. Daveau, G. Marchioro, C. Valderrama, M. Romdhani, T. Ben Ismail et al.
    Pages 133-158
  8. Don W. Bouldin
    Pages 179-210
  9. Hans G. Kerkhoff
    Pages 211-222
  10. Back Matter
    Pages 233-233

About this book


Design of Systems on a Chip: Design&Test is the second of two volumes addressing the design challenges associated with new generations of the semiconductor technology. The various chapters are the compilations of tutorials presented at workshops in the recent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip. In particular this second book include contributions on three different, but complementary axes: core design, computer-aided design tools and test methods. A collection of chapters deal with the heterogeneity aspect of core designs, showing the diversity of parts that may share the same substrate in a state-of-the-art system on a chip. The second part of the book discusses CAD in three different levels of design abstraction, from system level to physical design. The third part deals with test methods. The topic is addressed from different viewpoints: in terms of chip complexity, test is discussed from the core and system prospective; in terms of signal heterogeneity, the digital, mixed-signal and microsystem prospective are considered.

Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault tolerant techniques for programmable logic applications.


FPGA Field Programmable Gate Array Hardware automation circuit design automation gate array integrated circuit microprocessor microprocessors microsystems semiconductor software system on chip (SoC) testing

Editors and affiliations

  • Ricardo Reis
    • 1
  • Marcelo Lubaszewski
    • 2
  • Jochen A.G. Jess
    • 3
  1. 1.Federal University of Rio Grande do SulBrazil
  2. 2.Federal University of Rio Grande do SulBrazil
  3. 3.Department Of Electrical Engineering, Design Automation SectionEidhoven University of TechnologyEindhoven

Bibliographic information

Industry Sectors
IT & Software
Energy, Utilities & Environment
Oil, Gas & Geosciences