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Radioelectronics and Communications Systems

, Volume 61, Issue 12, pp 565–570 | Cite as

High Efficiency Cross-Coupled Charge Pump Circuit with Four-Clock Signals

  • Minglin MaEmail author
  • Xinglong Cai
  • Jin Jiang
  • Yichuang Sun
Article
  • 12 Downloads

Abstract

A fully integrated cross-coupled charge pump circuit for boosting dc-to-dc converter applications with four-clock signals has been proposed. With the new clock scheme, this charge pump eliminates all of the reversion power loss and reduces the ripple voltage. In addition, the largest voltage differences between the terminals of all transistors do not exceed the power supply voltage for solving the gate-oxide overstress problem in the conventional charge pump circuits and enhancing the reliability. This proposed charge pump circuit does not require any extra level shifter; therefore, the power efficiency is increased. The proposed charge pump circuit has been simulated using Spectre in the TSMC 0.18 μm CMOS process. The simulation results show that the maximum voltage conversion efficiency of the new 3-stage cross-coupled circuit with an input voltage of 1.5Vis 99.8%. According to the comparison results of the conventional pump and the enhanced charge pump proposed, the output ripple voltage has been significantly reduced.

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References

  1. 1.
    J. F. Dickson, “On–chip high–voltage generation in MNOS integrated circuits using an improved voltage multiplier technique,” IEEE J. Solid–State Circuits 11, No. 3, 374 (1976). DOI: 10.1109/JSSC.1976.1050739.CrossRefGoogle Scholar
  2. 2.
    J. T. Wu and K.–L. Chang, “MOS charge pumps for low–voltage operation,” IEEE J. Solid–State Circuits 33, No. 4, 592 (1998). DOI: 10.1109/4.663564.CrossRefGoogle Scholar
  3. 3.
    M.–D. Ker, S.–L. Chen, and C. S. Tsai, “Design of charge pump circuit with consideration of gate–oxide reliability in low–voltage CMOS processes,” IEEE J. Solid–State Circuits 41, No. 5, 1100 (2006). DOI: 10.1109/JSSC. 2006.872704.CrossRefGoogle Scholar
  4. 4.
    H. Lee and P. K. T. Mok, “Switching noise and shoot–through current reduction techniques for switched–capacitor voltage doubler,” IEEE J. Solid–State Circuits 40, No. 5, 1136 (2005). DOI: 10.1109/JSSC. 2005.845978.CrossRefGoogle Scholar
  5. 5.
    T. Das, S. Prasad, S. Dam, and P. Mandal, “A pseudo cross–coupled switch–capacitor based DC–DC boost converter for high efficiency and high power density,” IEEE Trans. Power Electronics 29, No. 11, 5961 (2014). DOI: 10.1109/TPEL.2014.2297972.CrossRefGoogle Scholar
  6. 6.
    J.–Y. Kim, S.–J. Park, K.–W. Kwon, B.–S. Kong, J.–S. Choi, and Y.–H. Jun, “CMOS charge pump with no reversion loss and enhanced drivability,” IEEE Trans. Very Large Scale Integration Systems 22, No. 6, 1441 (2014). DOI: 10.1109/TVLSI.2013.2267214.CrossRefGoogle Scholar
  7. 7.
    T. W. Mui, M. Ho, K. H. Mak, J. Guo, H. Chen, and K. N. Leung, “An area–efficient 96.5%–peak–efficiency cross–coupled voltage doubler with minimum supply of 0.8 V,” IEEE Trans. Circuits Systems II: Express Briefs 61, No. 9, 656 (2014). DOI: 10.1109/TCSII.2014.2331109.CrossRefGoogle Scholar

Copyright information

© Allerton Press, Inc. 2018

Authors and Affiliations

  1. 1.Xiangtan UniversityXiangtanChina
  2. 2.University of HertfordshireHatfieldUK

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