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Automatic Control and Computer Sciences

, Volume 53, Issue 1, pp 1–11 | Cite as

Using Codes with Summation of Weighted Bits to Organize Checking of Combinational Logical Devices

  • D. V. EfanovEmail author
  • V. V. Sapozhnikov
  • Vl. V. SapozhnikovEmail author
Article
  • 2 Downloads

Abstract

This article analyzes the peculiarities of applying weighted sum codes in tasks of building logical device check circuits for weighing of bits via random weighting coefficients, with check bits limited in number by the number of check bits of classical Berger codes. Important regularities typical of weighted sum codes are discovered. Weighted codes belong to codes that detect unidirectional errors (UED codes). The presented technique of synthesizing weighted sum codes allows creating the simplest structures of these devices based on the standard circuits of full adders and half adders of units. The main properties of weighted sum codes via error detection in information vectors and in outputs of combinational check circuits are confirmed via experiment.

Keywords:

combinational logical devices combinational device check check circuit Berger code weighted sum codes code characteristics adder check circuit 

Notes

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Copyright information

© Allerton Press, Inc. 2019

Authors and Affiliations

  1. 1.Russian University of TransportMoscowRussia
  2. 2.Emperor Alexander I Saint Petersburg State Transport UniversitySaint PetersburgRussia

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