Performance-driven assignment and mapping for reliable networks-on-chips
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Network-on-chip (NoC) communication architectures present promising solutions for scalable communication requests in large system-on-chip (SoC) designs. Intellectual property (IP) core assignment and mapping are two key steps in NoC design, significantly affecting the quality of NoC systems. Both are NP-hard problems, so it is necessary to apply intelligent algorithms. In this paper, we propose improved intelligent algorithms for NoC assignment and mapping to overcome the drawbacks of traditional intelligent algorithms. The aim of our proposed algorithms is to minimize power consumption, time, area, and load balance. This work involves multiple conflicting objectives, so we combine multiple objective optimization with intelligent algorithms. In addition, we design a fault-tolerant routing algorithm and take account of reliability using comprehensive performance indices. The proposed algorithms were implemented on embedded system synthesis benchmarks suite (E3S). Experimental results show the improved algorithms achieve good performance in NoC designs, with high reliability.
Key wordsNetwork-on-chip (NoC) Mapping Assignment Reliability
CLC numberTP202 TN402
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- Das, R., Eachempati, S., Mishra, A.K., et al., 2009. Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. Proc. IEEE 15th Int. Symp. on High Performance Computer Architecture, p.175–186. [doi:10.1109/HPCA.2009.4798252]Google Scholar
- Hu, J., Marculescu, R., 2003. Energy-aware mapping for tile-based NoC architectures under performance constraints. Proc. Asia and South Pacific Design Automation Conf., p.233–239. [doi:10.1109/ASPDAC.2003.1195022]Google Scholar
- Hung, W.N.N., Song, X., 2001. BDD variable ordering by scatter search. Proc. Int. Conf. on Computer Design, p.368–373. [doi:10.1109/ICCD.2001.955053]Google Scholar
- Jena, R.K., Sharma, G.K., 2007. A multi-objective evolutionary algorithm based optimization model for network-on-chip synthesis. Proc. 4th Int. Conf. on Information Technology, p.977–982. [doi:10.1109/ITNG.2007.10]Google Scholar
- Orgas, U.Y., Hu, J., Marculescu, R., 2005. Key research problems in NoC design: a holistic perspective. Proc. 3rd IEEE/ACM/IFIP Int. Conf. on Hardware/Software Codesign and System Synthesis, p.69–74. [doi:10.1145/1084834.1084856]Google Scholar
- Refan, F., Alemzadeh, H., Safari, S., et al., 2008. Reliability in application specific mesh-based NoC architectures. Proc. 14th IEEE Int. On-line Testing Symp., p.207–212. [doi:10.1109/IOLTS.2008.53]Google Scholar
- Sepulveda, M.J., Strum, M., Chau, W.J., 2011. A multi-objective adaptive immune algorithm for NoC mapping. Proc. 17th IFIP Int. Conf. on Very Large Scale Integration, p.193–196. [doi:10.1109/VLSISOC.2009.6041354]Google Scholar
- Tang, L., Kumar, S., 2003. A two-step genetic algorithm for mapping task graphs to a network on chip architecture. Euromicro Symp. on Digital System Design, p.180–187. [doi:10.1109/DSD.2003.1231923]Google Scholar
- Wang, J., Jiao, Y., Song, X., et al., 2012a. Optimal training sequences for indoor wireless optical communications. J. Opt., 14(1):015401.1–015401.5. [doi:10.1088/2040-8978/14/1/015401]Google Scholar