Skip to main content
Log in

Low-cost fault tolerance in evolvable multiprocessor systems: a graceful degradation approach

  • Science Letters
  • Published:
Journal of Zhejiang University-SCIENCE A Aims and scope Submit manuscript

Abstract

The evolvable multiprocessor (EvoMP), as a novel multiprocessor system-on-chip (MPSoC) machine with evolvable task decomposition and scheduling, claims a major feature of low-cost and efficient fault tolerance. Non-centralized control and adaptive distribution of the program among the available processors are two major capabilities of this platform, which remarkably help to achieve an efficient fault tolerance scheme. This letter presents the operational as well as architectural details of this fault tolerance scheme. In this method, when a processor becomes faulty, it will be eliminated of contribution in program execution in remaining run-time. This method also utilizes dynamic rescheduling capability of the system to achieve the maximum possible efficiency after processor reduction. The results confirm the efficiency and remarkable advantages of the proposed approach over common redundancy based techniques in similar systems.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  • Barker, W., Halliday, D.M., Thoma, Y., Sanchez, E., Tempesti, G., Tyrrell, A., 2007. Fault tolerance using dynamic reconfiguration on the POEtic tissue. IEEE Trans. Evol. Comput., 11(5):666–684. [doi:10.1109/TEVC.2007.896690]

    Article  Google Scholar 

  • Beitollahi, H., Deeconinick, G., 2006. Fault-tolerant Partitioning Scheduling Algorithms in Real-time Multiprocessor Systems. Proc. Pacific Rim Symp. on Dependable Computing, p.296–304. [doi:10.1109/PRDC.2006.34]

  • Canham, R., Tyrrell, A., 2003. An Embryonic Array with Improved Efficiency and Fault Tolerance. Proc. NASA/DoD Conf. on Evolvable Hardware, p.265–272. [doi:10.1109/EH.2003.1217678]

  • Manimaran, G., Murthy, C.S.R., 1998a. An efficient dynamic scheduling algorithm for multiprocessor real-time systems. IEEE Trans. Parall. Distrib. Syst., 9(3):312–319. [doi:10.1109/71.674322]

    Article  Google Scholar 

  • Manimaran, G., Murthy, C.S.R., 1998b. A fault-tolerant dynamic scheduling algorithm for multiprocessor real-time systems and its analysis. IEEE Trans. Parall. Distrib. Syst., 9(11):1137–1152. [doi:10.1109/71.735960]

    Article  Google Scholar 

  • Martin, G., 2005. Overview of the MPSoC Design Challenge. Proc. Design and Automation Conf., p.274–279.

  • Obermaisser, R., Kraut, H., Salloum, C., 2008. A Transientresilient System-on-a-chip Architecture with Support for On-chip and Off-chip TMR. Proc. Int. Dependable Computing Conf., p.123–134. [doi:10.1109/EDCC-7.2008.20]

  • Vakili, S., Fakhraie, S.M., Mohammadi, S., 2008. Designing an MPSoC Architecture with Run-time and Evolvable Task Decomposition and Scheduling: A Neural Network Case Study. 5th IEEE Int. Conf. on Innovations in Information Technology, p.106–110. [doi:10.1109/INNOVATIONS.2008.4781734]

  • Wolf, W., 2004. The Future of Multiprocessor Systems-onchips. Proc. Int. Design Automation Conf., p.681–685.

  • Zomaya, A.Y., Ward, C., Macey, B., 1999. Genetic scheduling for parallel processor systems: comparative studies and performance issues. IEEE Trans. Parall. Distrib. Syst., 10(8):795–812. [doi:10.1109/71.790598]

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Shervin Vakili.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Vakili, S., Fakhraie, S.M., Mohammadi, S. et al. Low-cost fault tolerance in evolvable multiprocessor systems: a graceful degradation approach. J. Zhejiang Univ. Sci. A 10, 922–926 (2009). https://doi.org/10.1631/jzus.A0820803

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1631/jzus.A0820803

Key words

CLC number

Navigation