In-package P/G planes analysis and optimization based on transmission matrix method
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Power integrity (PI) has become a limiting factor for the chip’s overall performance, and how to place in-package decoupling capacitors to improve a chip’s PI performance has become a hot issue. In this paper, we propose an improved transmission matrix method (TMM) for fast decoupling capacitance allocation. An irregular grid partition mechanism is proposed, which helps speed up the impedance computation and complies better with the irregular power/ground (P/G) plane or planes with many vias and decoupling capacitors. Furthermore, we also ameliorate the computation procedure of the impedance matrix whenever decoupling capacitors are inserted or removed at specific ports. With the fast computation of impedance change, in-package decoupling capacitor allocation is done with an efficient change based method in the frequency domain. Experimental results show that our approach can gain about 5× speedup compared with a general TMM, and is efficient in restraining the noise on the P/G plane.
Key wordsDecoupling capacitor Power/ground (P/G) planes Simultaneous switching noise (SSN) Transmission matrix method (TMM) Irregular partition Power integrity (PI)
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