An efficient prediction framework for multi-parametric yield analysis under parameter variations
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Due to continuous process scaling, process, voltage, and temperature (PVT) parameter variations have become one of the most problematic issues in circuit design. The resulting correlations among performance metrics lead to a significant parametric yield loss. Previous algorithms on parametric yield prediction are limited to predicting a single-parametric yield or performing balanced optimization for several single-parametric yields. Consequently, these methods fail to predict the multi-parametric yield that optimizes multiple performance metrics simultaneously, which may result in significant accuracy loss. In this paper we suggest an efficient multi-parametric yield prediction framework, in which multiple performance metrics are considered as simultaneous constraint conditions for parametric yield prediction, to maintain the correlations among metrics. First, the framework models the performance metrics in terms of PVT parameter variations by using the adaptive elastic net (AEN) method. Then the parametric yield for a single performance metric can be predicted through the computation of the cumulative distribution function (CDF) based on the multiplication theorem and the Markov chain Monte Carlo (MCMC) method. Finally, a copula-based parametric yield prediction procedure has been developed to solve the multi-parametric yield prediction problem, and to generate an accurate yield estimate. Experimental results demonstrate that the proposed multi-parametric yield prediction framework is able to provide the designer with either an accurate value for parametric yield under specific performance limits, or a multi-parametric yield surface under all ranges of performance limits.
Key wordsYield prediction Parameter variations Multi-parametric yield Performance modeling Sparse representation
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- Kaneda, S., Mizumoto, T., Maeno, T., et al., 2015. A cross validation of network system models for delay tolerant networks. Int. Conf. on Mobile Computing and Ubiqui-tous Networking, p.185–190. http://dx.doi.org/10.1109/ICMU.2015.7061064Google Scholar
- Mande, S.S., Chandorkar, A.N., Iwai, H., 2013. Computation-ally efficient methodology for statistical characterization and yield estimation due to inter-and intra-die process variations. Proc. 5th Asia Symp. on Quality Electronic Design, p.287–294. http://dx.doi.org/10.1109/ASQED.2013.6643602Google Scholar
- Nateghi, H., El-Sankary, K., 2015. A self-healing technique using ZTC biasing for PVT variations compensation in 65nm CMOS technology. Canadian Conf. on Electrical and Computer Engineering, p.128–131. http://dx.doi.org/10.1109/CCECE.2015.7129173Google Scholar
- Nelson, R.B., 2006. An Introduction to Copulas. Springer, New York. http://dx.doi.org/10.1007/0-387-28678-0Google Scholar
- Panchal, G., Ganatra, A., Kosta, Y.P., et al., 2010. Searching most efficient neural network architecture using Akaike’s information criterion (AIC). Int. J. Comput. Appl., 1(5):41–44. http://dx.doi.org/10.5120/126-242Google Scholar
- Srivastava, A., Chopra, K., Shah, S., et al., 2008. A novel approach to perform gate-level yield analysis and opti-mization considering correlated variations in power and performance. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst., 27(2):272–285. http://dx.doi.org/10.1109/TCAD.2007.907227CrossRefGoogle Scholar
- Visweswariah, C., 2003. Death, taxes and failing chips. Proc. 40th Annual Design Automation Conf., p.343–347. http://dx.doi.org/10.1145/775919.775921Google Scholar
- Xu, F., Li, C., Jiang, T., 2015. Printed circuit board model updating based on response surface method. J. Beijing Univ. Aeronaut. Astronaut., 41(3):449–455 (in Chinese).Google Scholar
- Yuan, X., 2009. Application Research of Markov Chain Sim-ulation in Reliability Analysis. PhD Thesis, Northwestern Polytechnical University, Xi’an, China (in Chinese).Google Scholar