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Design and simulation of a standing wave oscillator based PLL

Article

Abstract

A standing wave oscillator (SWO) is a perfect clock source which can be used to produce a high frequency clock signal with a low skew and high reliability. However, it is difficult to tune the SWO in a wide range of frequencies. We introduce a frequency tunable SWO which uses an inversion mode metal-oxide-semiconductor (IMOS) field-effect transistor as a varactor, and give the simulation results of the frequency tuning range and power dissipation. Based on the frequency tunable SWO, a new phase locked loop (PLL) architecture is presented. This PLL can be used not only as a clock source, but also as a clock distribution network to provide high quality clock signals. The PLL achieves an approximately 50% frequency tuning range when designed in Global Foundry 65 nm 1P9M complementary metal-oxide-semiconductor (CMOS) technology, and can be used directly in a high performance multi-core microprocessor.

Key words

Standing wave oscillator (SWO) Clock distribution Phase locked loop (PLL) Varactor 

CLC number

TN432 

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Copyright information

© Journal of Zhejiang University Science Editorial Office and Springer-Verlag Berlin Heidelberg 2016

Authors and Affiliations

  1. 1.State Key Lab of ASIC & SystemFudan UniversityShanghaiChina
  2. 2.Pack Vinn Excellence Center, School of ICTRoyal Institute of Technology (KTH) Eletrum 229Kista-StockholmSweden

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