An efficient bi-objective optimization framework for statistical chip-level yield analysis under parameter variations
With shrinking technology, the increase in variability of process, voltage, and temperature (PVT) parameters significantly impacts the yield analysis and optimization for chip designs. Previous yield estimation algorithms have been limited to predicting either timing or power yield. However, neglecting the correlation between power and delay will result in significant yield loss. Most of these approaches also suffer from high computational complexity and long runtime. We suggest a novel bi-objective optimization framework based on Chebyshev affine arithmetic (CAA) and the adaptive weighted sum (AWS) method. Both power and timing yield are set as objective functions in this framework. The two objectives are optimized simultaneously to maintain the correlation between them. The proposed method first predicts the guaranteed probability bounds for leakage and delay distributions under the assumption of arbitrary correlations. Then a power-delay bi-objective optimization model is formulated by computation of cumulative distribution function (CDF) bounds. Finally, the AWS method is applied for power-delay optimization to generate a well-distributed set of Pareto-optimal solutions. Experimental results on ISCAS benchmark circuits show that the proposed bi-objective framework is capable of providing sufficient trade-off information between power and timing yield.
KeywordsParameter variations Parametric yield Multi-objective optimization Chebyshev affine Adaptive weighted sum
- de Figueiredo, L.H., Stolfi, J., 2004. Affine arithmetic: concepts and applications. Numer. Algor., 37(1):147–158. http://dx.doi.org/10.1023/B:NUMA.0000049462.70970.b6MathSciNetCrossRefGoogle Scholar
- Kanj, R., Joshi, R., Nassif, S., 2010. Statistical leakage modeling for accurate yield analysis the CDF matching method and its alternatives. ACM/IEEE Int. Symp. on Low-Power Electronics and Design, p.337–342.Google Scholar
- Mande, S.S., Chandorkar, A.N., Iwai, H., 2013. Computationally efficient methodology for statistical characterization and yield estimation due to inter- and intra-die process variations. 5th Asia Symp. on Quality Electronic Design, p.287–294. http://dx.doi.org/10.1109/ASQED.2013.6643602Google Scholar
- Srivastava, A., Chopra, K., Shah, S., et al., 2008. A novel approach to perform gate-level yield analysis and optimization considering correlated variations in power and performance. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst., 27(2):272–285. http://dx.doi.org/10.1109/TCAD.2007.907227CrossRefGoogle Scholar