An efficient bi-objective optimization framework for statistical chip-level yield analysis under parameter variations
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Abstract
With shrinking technology, the increase in variability of process, voltage, and temperature (PVT) parameters significantly impacts the yield analysis and optimization for chip designs. Previous yield estimation algorithms have been limited to predicting either timing or power yield. However, neglecting the correlation between power and delay will result in significant yield loss. Most of these approaches also suffer from high computational complexity and long runtime. We suggest a novel bi-objective optimization framework based on Chebyshev affine arithmetic (CAA) and the adaptive weighted sum (AWS) method. Both power and timing yield are set as objective functions in this framework. The two objectives are optimized simultaneously to maintain the correlation between them. The proposed method first predicts the guaranteed probability bounds for leakage and delay distributions under the assumption of arbitrary correlations. Then a power-delay bi-objective optimization model is formulated by computation of cumulative distribution function (CDF) bounds. Finally, the AWS method is applied for power-delay optimization to generate a well-distributed set of Pareto-optimal solutions. Experimental results on ISCAS benchmark circuits show that the proposed bi-objective framework is capable of providing sufficient trade-off information between power and timing yield.
Keywords
Parameter variations Parametric yield Multi-objective optimization Chebyshev affine Adaptive weighted sumCLC number
TP3121 Introduction
Continuous process scaling has led to a large increase in process, voltage, and temperature (PVT) variability and a wide spread fluctuation in integrated circuit (IC) performance. This increasing variability brings significant impact on the parametric yield of today’s chip design (Mani et al., 2005; Radfar and Singh, 2014; Banerjee and Chatterjee, 2015). To be specific, 30% variation in effective channel length could cause over 20× fluctuation in leakage power (Rao et al., 2004a; Kanj et al., 2010). In addition, Srivastava et al. (2008) pointed out the negative correlation between power dissipation and timing performance of a design. This relationship causes significant yield loss when considering both power and timing limits and leads to a two-sided constraint over the design region.
Most of the previous yield estimation works have been limited to predicting either timing or leakage yield (Orshansky and Bandyopadhyay, 2004; Rao et al., 2004b; Xie and Davoodi, 2008). Dealing with only timing yield optimization will result in yield loss due to the power constraint (Srivastava et al., 2008). On the other hand, all the power yield analyses neglect the correlation between power and timing metrics. As mentioned above, in a chip design, the leakage power and delay are negatively correlated. This situation will consequently bring on a conflict between these two objectives during the optimization procedure and cause designers to be in a dilemma. Specifically, this situation has been more serious at a 20-nm technology node. Thus, there is a critical requirement to develop an effective approach that performs parametric yield optimization considering both power and timing constraints.
There is recent research focusing on considering power and timing metrics simultaneously in yield analysis and optimization. Hwang et al. (2003) proposed a novel statistical leakage minimization method using the timing yield slack for a gate change metric. This method can help improve not only the performance of leakage optimization but also the efficiency by providing valuable information to guide statistical leakage optimization. Based on optimal delay budgeting and slack utilization, Mani et al. (2007) presented a two-phase approach to solve the statistical leakage power minimization problem under timing yield constraints. The first phase is delay budgeting, which is formulated as a robust version of the power-weighted linear program that assigns slacks based on power-delay sensitivities of gates. The second phase consists of a local search among gate configurations in the library, such that slacks assigned to gates in the previous phase are used for power reduction. However, these approaches mentioned above fail to take into account the close correlation between leakage power and delay. They do not perform parametric yield optimization incorporating leakage and delay considerations, but optimize the power yield under timing constraints in the presence of variability.
Several research efforts have been made on optimizing yield in a multi-objective design fashion. For example, Liu et al. (2013) proposed a new timedomain performance bound analysis method for analog circuits, considering process variations. The method can give transient lower and upper bounds of the performance variations affected in analog circuits accurately and reliably. However, their approach requires additional computational cost for estimating yield specification from the predicted performance bounds. Additionally, it cannot handle parameter variations that are partially specified. Also, Guerra-Gómez et al. (2015) proposed several evolutionary algorithms to solve the multi-objective yield optimization problem. In their work, a strategy based on the optimal computing budget allocation approach was presented to reduce the simulation cost in the yield optimization of analog integrated circuits. However, their method cannot provide more flexibility in design trade-offs. In contrast, our work is discussed under the assumption of partially specified PVT parameter variations. It provides more flexibility and a simple optimization procedure with lower computation cost.
This study aims at solving the power-delay optimization problem by using multi-objective optimization techniques. The proposed optimization method incorporates leakage and delay considerations. We introduce a new power and timing yield optimization framework using Chebyshev affine arithmetic (CAA) and the adaptive weighted sum (AWS) method for multi-objective optimization. This framework treats both timing and power yield as objective functions and optimizes these two goals simultaneously. Additionally, because AWS is used for optimization in multi-domain, our framework can include extra objectives, e.g., area and thermal metrics. Different from traditional multi-objective optimization methods, our optimization methodology distributes the optimal solutions uniformly upon the Pareto front. As a result, it can provide the designers with multiple solutions distributed over the optimal design spectrum, giving designers the flexibility to choose the most appropriate solution(s) according to power and timing requirements.
The contributions of the new approach include: (1) maintaining the correlation between leakage power and delay by explicitly expressing both metrics in terms of the same parameter variations; (2) allowing arbitrary correlations among PVT parameters, because the yield prediction scheme for leakage power and delay is under the assumption of uncertain parameter correlations; and (3) providing designers with trade-off information between power and timing yield to find the best solution(s). The final result is a set of Pareto-optimal solutions uniformly distributed over the design region. The flexibility obtained by the new multi-objective framework was demonstrated on various ISCAS benchmark circuits. For each circuit, well-distributed sets of Pareto-optimal solutions were obtained by the proposed methodology.
2 Statistical leakage and delay model
This section discusses in detail the statistical models for leakage power and delay under the influence of parameter variations, which will be incorporated into the bi-objective model for optimization. Here, the variability in leakage and delay will be expressed as a function of several key PVT parameters. In this way, the correlation between power and delay is preserved for yield estimation, because they both depend on the identical underlying parameter variations.
Having established the statistical models of leakage power and delay in expressions of parameter variations, we are able to develop the power-delay bi-objective optimization framework, which will be described in the subsequent part. Note that leakage and delay are correlated due to their common dependence on identical PVT parameters.
3 Bi-objective optimization procedure
Guerra-Gómez et al. (2013) proposed a sensitivity analysis in the multi-objective optimization of analog circuits. The approach can achieve good accuracy for small design parameter perturbations or relatively linear behaviors in analog circuit performances. However, the leakage power in our optimization framework is highly nonlinear to design parameters. Thus, we must seek other yield prediction approaches that can handle nonlinear dependency upon parameter variations and limited descriptions of parameter variations.
This section applies the CAA method to address the above two issues and discusses how to formulate the proposed power-delay bi-objective optimization model to obtain a well-distributed set of Pareto-optimal solutions. First, the CAA methodology is applied to predict a guaranteed cumulative distribution function (CDF) bound for leakage power and delay based on the models described in Section 2. The distribution function directly provides the functional relationship between power/delay metrics and design parameters. Then leakage yield and timing yield functions can be established as two objective functions. Finally, the bi-objective optimization model for power and timing yield is proposed, which will be optimized in the subsequent part.
3.1 CAA-based probability bound prediction
The PVT parameter variations are assumed to be partially specified; i.e., only the mean and variance information may be available. As suggested in much literature, some PVT parameters tend to be uncertain or even have unknown distributions (Gong et al., 2011; Ukhov et al., 2014). Under this assumption, this study applies the CAA method to predict parametric yield robustly with fully or partially specified parameter variations.
The resulting CDF bounds obtained by Chebyshev approximation are named ‘piecewise linear probability bounds’ (PLPBs) (Sun et al., 2008). Given random variables in PLPB representations, an efficient prediction scheme can be provided for correlating CDF bounds under operations upon random variables. This scheme transforms all the non-affine operations into affine forms by Chebyshev approximation, and then CDF bounds are predicted step by step under affine operations, handling arbitrary correlations among variations.
3.2 Correlation CDF bound computation
Similarly, we can obtain the bounds for ‘subtract’, ‘multiply’, and ‘divide’ operations according to Williamson and Downs (1990). As ‘multiply’ and ‘divide’ operations are not used in this study, we do not consider them here.
Once the abovementioned bounds are obtained, affine operations Z=X±Y exhibit a functional relationship in the inverses of X’ and Y’s CDF bounds. Here, taking Eq. (11) as an example, for a fixed probability value p, if we assume \(g(u) = F_{{\rm{D}},X}^{ - 1}(u) + F_{{\rm{D}},Y}^{ - 1}(p - u + 1)\), then \(F_{{\rm{D}},X + Y}^{ - 1}(p)\) is obviously the minimum value of g(u) in the interval [p, 1]. To solve this optimization problem, we will represent random variables in PLPB formation. It can propose a simple optimization procedure with low computation cost.
3.3 Bi-objective optimization model
In chip-level parametric yield analysis, a reasonable assumption is that each device has a unique intra-chip variation ΔP_{intra} while sharing the same inter-chip variation ΔP_{inter} with all other devices. Therefore, global process variations may be regarded as fixed values for each device. All process variations are fully specified by corresponding CDFs, while all environmental variations are partially specified by the corresponding mean and variance values. The corresponding PLPB representations can be constructed conveniently by Chebyshev approximation.
According to Eqs. (4) and (6), the leakage power and gate delay for a chip design are represented as functions in terms of PVT parameter variations. Using the CAA methodology, we can finally obtain a guaranteed CDF bound for leakage power or delay distribution. Taking the delay model as an example, it is already in the affine form according to Eq. (8). Within several steps, CAA is able to predict the upper and lower probability bounds for delay distribution under parameter variations. Regardless of relationship among PVT parameters, any CDF generated under an arbitrary correlation situation will be enclosed by CAA predicted bounds. As our purpose is to optimize the guaranteed parametric yield, we consider only the lower probability bound, which is denoted by F_{D}. There will be a similar conclusion for power distribution. In the leakage model, two CAA approximations, quadratic and exponential operations, are required to reduce the leakage function to a series of affine operations on parameter variations. The guaranteed (lower) CDF bound for leakage distribution, generated in the same manner, is denoted by F_{L}.
So far we have established the functional relationship between parametric yield and design parameters x ∈ [L, V_{th}, T_{ox}, V_{dd}, T], because leakage and delay distributions both depend on the variability in parameters.
The algorithmic flow of CAA-based yield prediction is summarized in Algorithm
:In Algorithm (4) and (6). Having the explicit expressions of leakage power and gate delay parameterized with design parameters, the ‘Non_Affine_Check’ subroutine identifies the affine operations and non-affine operations in analytical power and timing models, denoted by op_NonAff and op_Aff, respectively. The ‘Chebyshev_Approx’ and ‘Combine’ subroutines further translate the power or delay model into a sequence of affine operations and put them into a stack, op_Stack. The ‘CDF_Generation’ subroutine returns the CDF bounds represented by PLPB, denoted by dummy_CDF. The ‘PUSH’ subroutine is the push operation to push the dummy_CDF into the stack, CDF_Stack; the ‘POP’ subroutine is the pop operation. The ‘CAA_Bound_Computation’ subroutine is responsible for generating the correlation CDF bound under a specified affine operation. By repeatedly performing the ‘CAA_Bound_Computation’ subroutine, the algorithm predicts the distribution information for power and timing metrics which are represented by ‘Distribution’. Then the ‘Prob’ subroutine returns the parametric yield by computing the CDF value at limit M_{0}. he resulting power yield Y_{L} and timing yield Y_{D} are determined as two objective functions in our bi-objective optimization framework.
, the ‘Model_Extraction’ subroutine returns the expressions demonstrated in Eqs.4 AWS-based bi-objective optimization
The adaptive weighted sum method (Kim and de Weck, 2005) is a methodology that effectively determines the Pareto front for a multi-objective optimization problem. It can produce well-distributed Pareto-optimal solutions by changing the weights adaptively. In this work, the AWS method is used to address the power-delay bi-objective optimization issue considering both leakage and delay limits.
4.1 Pareto-optimality
In a multi-optimization framework, the objective function \(f(x) = [{f_1}(x),{f_2}(x),\; \ldots ,\;{f_n}(x)]\) often conflicts with each other (Kashfi et al., 2011), such as the leakage power and delay in a circuit design. For conflicting objectives, it is not feasible to optimize the performance for all of them; improving one will result in deteriorating another. In such a case, we strive for Pareto-optimality that ensures the best overall performance. Here, a Pareto-optimal solution can be defined as follows (Srinivas and Deb, 1994; Li and Lian, 2008; Lourenco and Horta, 2012): Definition 1 (Pareto-optimal solution) (Li and Lian, 2008) Given u* ∈ U, if \(\neg \exists u \in U\) s.t. \(u \prec {u^\ast},{u^\ast}\) is said to be a Pareto-optimal solution.
The surface consisting of the complete set of Pareto-optimal solutions in the objective space is then called the Pareto-optimal front.
In this work, the optimization problem can be attributed as a bi-objective issue (it can, however, be extended to the multi-optimization case) whose two objectives are power and timing yield. AWS is an adaptive approach for multi-objective optimization. Different from the traditional weighted sum method, the weighting factor in AWS is not predetermined but evolves according to the nature of the Pareto front. By updating the weighting factor adaptively, AWS focuses on unexplored regions where no solution can be obtained by the traditional method; therefore, it is able to extract new Pareto-optimal solutions in these regions and generate a well-distributed Pareto front (Kim and de Weck, 2005).
4.2 Bi-objective optimization procedure
Take Y_{L}′ as an example. Assume x_{1}^{*} and x_{2}^{ * } are the optimal solutions for the single objective optimization of Y_{L} and Y_{D}, respectively. Then, Y_{L}^{U} can be obtained by Y_{L}^{U} = Y_{L}(x_{1}^{ * }), and Y_{L}^{N} is determined by \(Y_{\rm{L}}^{\rm{N}} = \max [{Y_{\rm{L}}}(x_1^\ast ),{Y_{\rm{D}}}(x_2^\ast )]\). Normalized Y_{D}′ can be obtained in the same manner. The uniform step size of the weighing factor α is set as Δα=1/n_{0}, where n_{0} is the number of divisions (typically, n_{0}=5–10). By changing the weighting factor α according to the step size Δα, a small set of optimal solutions for problem (18) will be obtained.
The regions in the power-delay objective space that need further refinement can be identified by computing the distances between adjacent solutions. If the distance is smaller than a preset value, no further refinement will be conducted in this region. Otherwise, the region with the long distance between adjacent solutions becomes a feasible region in which new solutions should be extracted. New solution extraction is implemented by imposing additional inequality constraints and solving a sub-optimization problem (Kim and de Weck, 2005).
The two objective functions in problem (18), power yield and timing yield, have been established by the yield prediction procedure in Section 3. The first step is to generate the first round solutions using the traditional weighted sum method. By setting Δα, a small set of solutions is specified. These are not close enough to form a well-distributed Pareto front. By calculating the distances between adjacent solutions, we identify two feasible regions where extraction of a new solution is necessary (Fig. 6a).
In each region, with Δα_{ i } substituted into Eq. (21), a set of new solutions is generated by solving this sub-optimization problem (Fig. 6b). Now the Pareto solutions are uniformly distributed on the Pareto front.
5 Experimental results
This section presents the results of the proposed bi-objective optimization framework. The computer used to perform all experiments has a quad-core 2.5 GHz CPU and a 4 GB RAM. The coefficients in the leakage model and delay model are determined by HSPICE simulations. Here, according to the empirical data in Visweswariah (2003), we model the process variations as truncated Gaussian distributions. The 3σ values of effective channel length, threshold voltage, and oxide thickness are 20%, 10%, and 8% of the nominal values, respectively. The inter- and intra-chip variations of the process parameters account for 50%, respectively. With regard to environmental parameters, power-supply voltage and on-chip temperature are assumed as being distributed uniformly. The nominal values of voltage and temperature are 1.1 V and 25 °C, respectively. The maximum voltage drop is 0.11 V (10% of the nominal value). The maximum deviation on on-chip temperature is 10 °C. The effectiveness of the algorithm is evaluated by using ISCAS benchmark circuits.
Having verified the reliability of CAA predicted probability bounds, we can perform the proposed power-delay bi-objective optimization procedure based on the predicted leakage distribution F_{L} and delay distribution F_{D}. It needs to be indicated that leakage power exhibits a greater sensitivity than gate delay. Larger spread in leakage variability can be observed in Fig. 7. This difference is due to the exponential term in the leakage model, which propagates significant fluctuation in leakage power.
A few Pareto-optimal solutions obtained by AWS for parametric yield
Circuit name | Number of solutions | Power yield | Timing yield | Runtime (s) | ||||
---|---|---|---|---|---|---|---|---|
α=1.0 | α=0.5 | α=0 | α=1.0 | α=0.5 | α=0 | |||
C432 | 21 | 0.9947 | 0.8176 | 0.1037 | 0.9370 | 0.9608 | 0.9883 | 41 |
C499 | 21 | 0.9947 | 0.8200 | 0.1037 | 0.9209 | 0.9479 | 0.9797 | 37 |
C880 | 18 | 0.9947 | 0.6987 | 0.0180 | 0.9568 | 0.9788 | 0.9844 | 81 |
C1335 | 20 | 0.9940 | 0.8171 | 0.1034 | 0.9474 | 0.9688 | 0.9893 | 85 |
C1908 | 23 | 0.9943 | 0.8507 | 0.0182 | 0.9054 | 0.9161 | 0.9446 | 106 |
C2670 | 20 | 0.9942 | 0.8200 | 0.0179 | 0.9326 | 0.9554 | 0.9672 | 148 |
C3540 | 22 | 0.9947 | 0.8199 | 0.1037 | 0.9369 | 0.9595 | 0.9506 | 201 |
C5315 | 23 | 0.9947 | 0.1037 | 0.0181 | 0.9163 | 0.9709 | 0.8741 | 253 |
C6288 | 23 | 0.9946 | 0.1037 | 0.0179 | 0.9283 | 0.9652 | 0.9611 | 361 |
C7552 | 21 | 0.9947 | 0.1036 | 0.0181 | 0.9359 | 0.9850 | 0.9707 | 373 |
A few Pareto-optimal solutions obtained by AWS for yield percentile
Circuit name | Number of solutions | Leakage (95%) | Delay (95%) | Runtime (s) | ||||
---|---|---|---|---|---|---|---|---|
α=1.0 | α=0.5 | α=0 | α=1.0 | α=0.5 | α=0 | |||
C432 | 15 | 1.071 | 1.262 | 1.740 | 1.029 | 1.072 | 0.989 | 41 |
C499 | 15 | 1.070 | 1.197 | 1.738 | 1.039 | 1.025 | 0.998 | 37 |
C880 | 14 | 1.070 | 1.355 | 1.739 | 1.015 | 0.997 | 0.979 | 81 |
C1335 | 14 | 1.071 | 1.479 | 1.740 | 1.022 | 0.996 | 0.985 | 85 |
C1908 | 15 | 1.070 | 1.245 | 1.739 | 1.047 | 1.033 | 1.008 | 106 |
C2670 | 15 | 1.069 | 1.240 | 1.739 | 1.031 | 1.017 | 0.994 | 148 |
C3540 | 15 | 1.070 | 1.257 | 1.740 | 1.029 | 1.014 | 0.991 | 201 |
C5315 | 15 | 1.070 | 1.264 | 1.740 | 1.043 | 1.028 | 1.005 | 253 |
C6288 | 15 | 1.070 | 1.428 | 1.739 | 1.040 | 1.019 | 1.005 | 361 |
C7552 | 14 | 1.071 | 1.254 | 1.740 | 1.030 | 1.015 | 0.991 | 373 |
6 Conclusions
This paper proposes a novel power-delay bi-objective optimization methodology for statistical yield optimization. Regarding both power and timing yield as objective functions, an efficient bi-objective optimization framework is suggested to optimize these two goals simultaneously under PVT parameter variations. The proposed algorithm was verified using ISCAS benchmark circuits, demonstrating its efficiency.
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