An efficient bi-objective optimization framework for statistical chip-level yield analysis under parameter variations



With shrinking technology, the increase in variability of process, voltage, and temperature (PVT) parameters significantly impacts the yield analysis and optimization for chip designs. Previous yield estimation algorithms have been limited to predicting either timing or power yield. However, neglecting the correlation between power and delay will result in significant yield loss. Most of these approaches also suffer from high computational complexity and long runtime. We suggest a novel bi-objective optimization framework based on Chebyshev affine arithmetic (CAA) and the adaptive weighted sum (AWS) method. Both power and timing yield are set as objective functions in this framework. The two objectives are optimized simultaneously to maintain the correlation between them. The proposed method first predicts the guaranteed probability bounds for leakage and delay distributions under the assumption of arbitrary correlations. Then a power-delay bi-objective optimization model is formulated by computation of cumulative distribution function (CDF) bounds. Finally, the AWS method is applied for power-delay optimization to generate a well-distributed set of Pareto-optimal solutions. Experimental results on ISCAS benchmark circuits show that the proposed bi-objective framework is capable of providing sufficient trade-off information between power and timing yield.


Parameter variations Parametric yield Multi-objective optimization Chebyshev affine Adaptive weighted sum 

CLC number



  1. Banerjee, A., Chatterjee, A., 2015. Signature driven hierarchical post-manufacture tuning of RF systems for performance and power. IEEE Trans. VLSI Syst., 23(2): 342–355. Scholar
  2. de Figueiredo, L.H., Stolfi, J., 2004. Affine arithmetic: concepts and applications. Numer. Algor., 37(1):147–158. Scholar
  3. Gong, F., Yu, H., He, L., 2011. Stochastic analog circuit behavior modeling by point estimation method. Proc. Int. Symp. on Physical Design, p.175–182. Scholar
  4. Guerra-Gómez, I., Tlelo-Cuautle, E., de la Fraga, L., 2013. Richardson extrapolation-based sensitivity analysis in the multi-objective optimization of analog circuits. Appl. Math. Comput., 222:167–167. Scholar
  5. Guerra-Gómez, I., Tlelo-Cuautle, E., de la Fraga, L., 2015. OCBA in the yield optimization of analog integrated circuits by evolutionary algorithms. IEEE Int. Symp. on Circuits & Systems, p.1933–1936. Scholar
  6. Hwang, E.J., Kim, W., Kim, Y.H., 2013. Timing yield slack for timing yield-constrained optimization and its application to statistical leakage minimization. IEEE Trans. VLSI Syst., 21(10):1783–1796. Scholar
  7. Kanj, R., Joshi, R., Nassif, S., 2010. Statistical leakage modeling for accurate yield analysis the CDF matching method and its alternatives. ACM/IEEE Int. Symp. on Low-Power Electronics and Design, p.337–342.Google Scholar
  8. Kashfi, F., Hatami, S., Pedram, M., 2011. Multi-objective optimization techniques for VLSI circuits. 12th Int. Symp. on Quality Electronic Design, p.156–163. Scholar
  9. Kim, I.Y., de Weck, O.L., 2005. Adaptive weighted-sum method for bi-objective optimization: Pareto front generation. Struct. Multidiscipl. Optim., 29(2):149–158. Scholar
  10. Li, H., Lian, J., 2008. Multi-objective optimization of watersedimentation-power in reservoir based on Paretooptimal solution. Trans. Tianjin Univ., 14(4):282–288. Scholar
  11. Liu, X.X., Tan, S.X.D., Palma-Rodriguez, A.A., et al., 2013. Performance bound analysis of analog circuits in frequency- and time-domain considering process variations. ACM Trans. Des. Autom. Electron. Syst., 19(1): 1–22. Scholar
  12. Lourenço, N., Horta, N., 2012. GENOM-POF: multi-objective evolutionary synthesis of analog ICs with corners validation. Proc. 14th Int. Conf. on Genetic and Evolutionary Computation, p.1119–1126. Scholar
  13. Mande, S.S., Chandorkar, A.N., Iwai, H., 2013. Computationally efficient methodology for statistical characterization and yield estimation due to inter- and intra-die process variations. 5th Asia Symp. on Quality Electronic Design, p.287–294. Scholar
  14. Mani, M., Devgan, A., Orshansky, M., 2005. An efficient algorithm for statistical minimization of total power under timing yield constraints. Proc. Design Automation Conf., p.309–314. Scholar
  15. Mani, M., Devgan, A., Orshansky, M., et al., 2007. A statistical algorithm for power- and timing-limited parametric yield optimization of large integrated circuits. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst., 26(10):1790–1802. Scholar
  16. Orshansky, M., Bandyopadhyay, A., 2004. Fast statistical timing analysis handling arbitrary delay correlations. Proc. 41st Annual Design Automation Conf., p.337–342. Scholar
  17. Radfar, M., Singh, J., 2014. A yield improvement technique in severe process, voltage, and temperature variations and extreme voltage scaling. Microelectron. Reliab., 54(12): 2813–2823. Scholar
  18. Rao, R., Devgan, A., Blaauw, D., et al., 2004a. Parametric yield estimation considering leakage variability. Proc. 41st Annual Design Automation Conf., p.442–447. Scholar
  19. Rao, R., Srivastava, A., Blaauw, D., et al., 2004b. Statistical analysis of subthreshold leakage current for VLSI circuits. IEEE Trans. VLSI Syst., 12(2):131–139. Scholar
  20. Saad, A., Frühwirth, T., Gervet, C., 2014. The p-box CDF-intervals: a reliable constraint reasoning with quantifiable information. Theory Pract. Log. Programm., 14(4–5):461–475. Scholar
  21. Sheng, Y., Xu, K., Wang, D., et al., 2013. Performance analysis of FET microwave devices by use of extended spectralelement time-domain method. Int. J. Electron., 100(5): 699–717. Scholar
  22. Srinivas, N., Deb, K., 1994. Multi-objective optimization using non-dominated sorting in genetic algorithms. Evol. Comput., 2(3):221–248. Scholar
  23. Srivastava, A., Chopra, K., Shah, S., et al., 2008. A novel approach to perform gate-level yield analysis and optimization considering correlated variations in power and performance. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst., 27(2):272–285. Scholar
  24. Sun, J., Huang, Y., Li, J., et al., 2008. Chebyshev affine arithmetic based parametric yield prediction under limited descriptions of uncertainty. Proc. Asia and South Pacific Design Automation Conf., p.531–536. Scholar
  25. Ukhov, I., Eles, P., Peng, Z., 2014. Probabilistic analysis of power and temperature under process variation for electronic system design. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst., 33(6):931–944. Scholar
  26. Visweswariah, C., 2003. Death, taxes and falling chips. Proc. Design Automation Conf., p.343–347. Scholar
  27. Wang, W.S., Orshansky, M., 2006. Robust estimation of parametric yield under limited descriptions of uncertainty. Proc. IEEE/ACM Int. Conf. on Computer-Aided Design, p.884–890. Scholar
  28. Williamson, R.C., Downs, T., 1990. Probabilistic arithmetic. I. numerical methods for calculating convolutions and dependency bounds. Int. J. Approx. Reason., 4(2):89–158. Scholar
  29. Xie, L., Davoodi, A., 2008. Robust estimation of timing yield with partial statistical information on process variations. 9th Int. Symp. on Quality Electronic Design, p.156–161. Scholar
  30. Zhu, W., Wu, Z., 2014. The stochastic ordering of meanpreserving transformations and its applications. Eur. J. Oper. Res., 239(3):802–809. Scholar

Copyright information

© Journal of Zhejiang University Science Editorial Office and Springer-Verlag Berlin Heidelberg 2016

Authors and Affiliations

  1. 1.Technology Innovation CenterJiangsu Academy of Safety Science and TechnologyNanjingChina
  2. 2.Jiangsu High Technology Research Key Laboratory for Wireless Sensor NetworksNanjing University of Posts and TelecommunicationsNanjingChina
  3. 3.School of Computer Science and EngineeringNanjing University of Science and TechnologyNanjingChina

Personalised recommendations