Pentagate Approach to Reduce the Line Edge Roughness Effects in Bulk Si Tri-gate Transistors

Abstract

Accumulated body [1] approach to mitigate the effects of line edge roughness on bulk silicon finFETs and tri-gate FETs is analyzed through 3D TCAD simulations. A side-gate surrounding the body portion of the FET is used to accumulate the body with majority carriers. This approach is predicted to reduce device-to-device variability due to line edge roughness by stronger accumulation of the body in the wider sections of the channel and confinement of the channel away from the edges.

This is a preview of subscription content, access via your institution.

References

  1. [1]

    A. Gokirmak and S. Tiwari, “Accumulated body ultranarrow channel silicon transistor with extreme threshold voltage tunability “ Appl. Phys. Lett., vol. 91, pp. 243504, 2007.

    Article  Google Scholar 

  2. [2]

    A. Asenov, S. Kaya and A. R. Brown, “Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness,” Electron Devices, IEEE Transactions on, vol. 50, pp. 1254–1260, 2003.

    CAS  Article  Google Scholar 

  3. [3]

    E. Baravelli, A. Dixit, R. Rooyackers, M. Jurczak, N. Speciale and K. De Meyer, “Impact of Line-Edge Roughness on FinFET Matching Performance,” Electron Devices, IEEE Transactions on, vol. 54, pp. 2466–2474, 2007.

    Article  Google Scholar 

  4. [4]

    M. L. Fan, Y. S. Wu, V. P. Hu, C. Y. Hsieh, P. Su and C. T. Chuang, “Comparison of 4T and 6T FinFET SRAM Cells for Subthreshold Operation Considering Variability—A Model-Based Approach,” Electron Devices, IEEE Transactions on, vol. 58, pp. 609–616, 2011.

    Article  Google Scholar 

  5. [5]

    C. R. M. Struck, M. J. Neumann, R. Raju, R. L. Bristol and D. N. Ruzic, “Grazing incidence ion beams for reducing LER,” in 2008, pp. 71402P.

  6. [6]

    S. Bangsaruntip, G. M. Cohen, A. Majumdar, Y. Zhang, S. U. Engelmann, N. Fuller, L. M. Gignac, S. Mittal, J. S. Newbury, M. Guillorn, T. Barwicz, L. Sekaric, M. M. Frank and J. W. Sleight, “High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling,” in Electron Devices Meeting (IEDM), 2009 IEEE International, 2009, pp. 1–4.

  7. [7]

    Synopsys Inc., “Sentaurus TCAD User Manual,” 2011.

Download references

Author information

Affiliations

Authors

Corresponding author

Correspondence to Mustafa B. Akbulut.

Rights and permissions

Reprints and Permissions

About this article

Cite this article

Akbulut, M.B., Silva, H. & Gokirmak, A. Pentagate Approach to Reduce the Line Edge Roughness Effects in Bulk Si Tri-gate Transistors. MRS Online Proceedings Library 1510, 11 (2013). https://doi.org/10.1557/opl.2013.529

Download citation