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High Yield Polymer MEMS Process for CMOS/MEMS Integration

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Abstract

MEMS community is increasingly using SU-8 as a structural material because it is self-patternable, compliant and needs a low thermal budget. While the exposed layers act as the structural layers, the unexposed SU-8 layers can act as the sacrificial layers, thus making it similar to a surface micromachining process. A sequence of exposed and unexposed SU-8 layers should lead to the development of a SU-8 based MEMS chip integrated with a pre-processed CMOS wafer. A process consisting of optical lithography to obtain SU-8 structures on a CMOS wafer is described in this paper.

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Authors and Affiliations

  1. Centre of Excellence in Nanoelectronics, Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India

    Prasenjit Ray, V. Seena, Prakash R. Apte & Ramgopal Rao

Authors
  1. Prasenjit Ray
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  2. V. Seena
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  3. Prakash R. Apte
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  4. Ramgopal Rao
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Ray, P., Seena, V., Apte, P.R. et al. High Yield Polymer MEMS Process for CMOS/MEMS Integration. MRS Online Proceedings Library 1299, 412 (2011). https://doi.org/10.1557/opl.2011.58

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  • DOI: https://doi.org/10.1557/opl.2011.58

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