In this paper new materials and substrate approaches are discussed which have potential to provide (Al)GaN buffers with a better crystal quality, higher critical electrical field, or thickness and have the potential to offer co-integration of GaN switches at different reference potentials, while maintaining lower wafer bow and maintaining complementary metal-oxide semiconductor (CMOS) compatibility. Engineered silicon substrates, silicon on insulator (SOI) and coefficient of thermal expansion (CTE)-matched substrates have been investigated and benchmarked with respect to each other. SOI and CTE-matched offer benefits for scaling to higher voltage, while a trench isolation process combined with an oxide interlayer substrate allows co-integration of GaN components in a GaN-integrated circuit (IC).
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Part of this work has been performed under collaboration between imec, QROMIS (Santa Clara, California, USA), and Aixtron (Aachen, Germany).
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Stoffels, S., Geens, K., Li, X. et al. Evaluation of novel carrier substrates for high reliability and integrated GaN devices in a 200 mm complementary metal-oxide semiconductor compatible process. MRS Communications 8, 1387–1394 (2018). https://doi.org/10.1557/mrc.2018.192