Material engineering for silicon tunnel field-effect transistors: isoelectronic trap technology


The tunnel field-effect transistor (TFET) is one of the candidates replacing conventional metal–oxide–semiconductor field-effect transistors to realize low-power-consumption large-scale integration (LSI). The most significant issue in the practical application of TFETs concerns their low tunneling current. Si is an indirect-gap material having a low band-to-band tunneling probability and is not favored for the channel. However, a new technology to enhance tunneling current in Si-TFETs utilizing the isoelectronic trap (IET) technology was recently proposed. IET technology provides a new approach to realize low-power-consumption LSIs with TFETs. The present paper reviews the state-of-the-art research and future prospects of Si-TFETs with IET technology.


The performance improvement of large-scale integration (LSI) has progressed owing to the miniaturization of transistors. The degree of integration has increased following Moore’slaw, which predicted that the number of components in LSI would doubles every 2 years.[1,2] This prediction has surprisingly come true since—the semiconductor industry has made constant efforts to continue satisfying the law. The increase in the number of transistors has been directly linked to the growth of computing performance, and such continuous improvement of computing performance has been realized over the last 70 years.

Koomey et al. examined the strong correlation between computing performance and power efficiency of computation.[3] Their work showed that the improvement of power efficiency is essential for the improvement of computing performance. From the perspective of electronic devices, the improvement of power consumption of transistors paved the way to increase the available number of transistors with a limited power supply, which resulted in the successful improvement of computing performance. In other words, low-power consumption is the essence of transistor miniaturization. This has enabled us to realize outstanding applications such as notebook personal computers, smartphones, tablets, and so on.

Dennard scaling guided the miniaturization of metal-oxide-semiconductor field-effect transistors (MOSFETs), which are the building blocks of contemporary LSIs.[4] Dennard scaling provides guidelines to reduce the power consumption of MOSFETs with device-size miniaturization. However, Dennard scaling is not valid any longer for the state-of-the-art MOSFETs, because of short-channel effects.[5] However, the semiconductor industry has achieved both miniaturization and the reduction of power consumption after the era of Dennard scaling, in which the key technologies were finFETs,[6] SOI-FETs,[7] and high-k technology[8] to enhance electrostatic gate control. In the current situation, the scaling law seems to have been prolonged, but some new technologies have realized miniaturization and low-power consumption together.

Now, we are at the last stage ofminiaturization. However, the enhancement of computing performance is still a demand because of new applications such as machine learning and artificial intelligence. In this situation, the reduction of power consumption must be continued even if miniaturization has been completed.

An approach to reduce the power consumption without miniaturization is the use of steep slope devices (SSDs) as new building blocks for LSIs instead of MOSFETs. SSDs can realize much steeper switching from the OFF to ON state, resulting in decreasing voltage for switching. MOSFETs have a physical limit that the subthreshold swing (SS) cannot be < 60 mV/decade at 300 K.[9] SSDs can operate with an SS < 60 mV/decade; thus, they can operate at a lower voltage compared with the operating voltage of MOSFETs, resulting in low-power consumption. Some existing candidates for SSDs are tunnel field-effect transistors (TFETs),[10] negative capacitance FETs,[11] and threshold switches.[12]

This paper concerns TFETs, which are a type of gated p-i-n diodes and have MOSFET-like structures in which the source and drain show different types of conduction. In TFETs, the tunnel barrier is a pn junction at the source side edge of the gate. The gate electrostatic control regulates tunneling current flowing through the barrier by changing the thickness of the pn junction, which enables TFETs to realize steeper switching compared with that of MOSFETs. Stuetzer’s and Shockley’s experiments have formed the foundation of TFET-like devices.[13,14] Modern TFETs having the MOS structure were proposed by Quinn et al.[15] and independently demonstrated by Baba.[16] Appenzeller et al. first demonstrated sub-60 mV/decade operation using a carbon-nanotube TFET.[17] Choi et al. first demonstrated sub-60 mV/decade operation in Si-TFETs.[18] Since then, many research groups have reported sub-60 mV/decade operation of Si-TFETs.[1924]

The low ON current (ION) is the most significant issue in TFET research. The ION of TFETs is still not sufficient for practically fast circuit operation. TFETs inherently have a highresistance tunneling barrier. As the tunneling current is essentially related to material science, many TFETs with new materials, including not only Ge or III-V materials[25] but also two-dimensional semiconductors,[26] have been reported. Recently, a material engineering technique to enhance tunneling current in Si has been proposed, which utilizes isoelectronic traps (IETs),[27,28] Experimental demonstrations of the current enhancement and improvement of circuit performance have been reported,[27,29] in which IET-assisted tunneling (IETT) is utilized instead of conventional band-to-band tunneling (BTBT).

This paper reviews the IET technology to enhance ION in Si-TFETs. General issues concerning TFETs have been reviewed in.[10,30] First, we present an overview of the state-of-the-art TFET research. Then, we examine the IET technology for Si-TFETs.

Overview of state-of-the-art TFET research

Guidelines to enhance BTBT

Before starting to discuss IET technology, we briefly discuss the conventional guidelines to improve TFET performance, aiming to summarize the background of the IET technology.

BTBT through a pn junction is categorized as Esaki tunneling under a forward bias or as Zener tunneling under a reverse bias. TFETs utilize Zener tunneling [Fig. 1(a)]. We begin with the equation of tunneling current flowing through a junction sandwiched between two electrodes[31]:

Figure 1.

(a) Schematic band diagrams for a pn diode. (b) Schematic views of indirect and direct processes for Zener tunneling. The E–k relationship is superimposed on band diagrams. (c) Density of states for free electrons in 3D, 2D, and 1D systems. (d) Tunneling rates for typical semiconductors calculated with Eqs. (3)(5).

$$I \propto \int {\left[ {{f_1}\left( E \right) - {f_2}\left( E \right)} \right]} {\left| M \right|^2}{D_1}\left( E \right){D_2}\left( E \right)dE,$$

where f(E) is a Fermi function, M is a transfer matrix element for transition, and D(E) is a density-of-state (DOS) function. Tunneling is a transition between two states. Thus, M can be expressed following Fermi’ s golden rule as

$${\left| M \right|^2} \propto {\left| {\left\langle {{\psi _2}\left| { - Fx} \right|{\psi _2}} \right\rangle } \right|^2},$$

where ψ is a wave function and the perturbative transition Hamiltonian is −Fx, in which F is the strength of the electric field at the junction, and x is the electron coordinate along the tunneling direction. In the case of BTBT through a pn junction, ψ1 is the state of valence band maximum (VBM), and ψ2 is that of conduction band minimum (CBM).

Equation (2) provides the first guideline to enhance tunneling current in TFETs: we should aim to increase the value of the integral on the right-hand side of the equation. Among conventional semiconductor materials used in electronic devices, which have crystal structures such as diamond, zincblende, and wurtzite, direct-band gap semiconductors, such as InGaAs, have a p-like VBM state and an s-like CBM state. Here the integral on the right-hand side of Eq. (2) has a significant value. In contrast, indirect-gap semiconductors, such as Si, have p-like CBM and VBM states, because of which the integral on the right-hand side has an insignificant value [Fig. 1(b)]. In indirect-gap semiconductors, as in the case of luminescence, phonon-assisted indirect tunneling occurs; however, its transition probability is lower than that of direct tunneling. This situation can be understood as the wave-number conservation rule. However, the indirect Ge case, in which direct tunneling occurs because the direct gap energy is close to the indirect gap energy, is complicated.[32] The direct/indirect tunneling current can be experimentally distinguished by temperature-dependent electric measurements.[28]

The second guideline is related to DOS, as expressed in Eq. (1). A higher DOS results in a higher tunneling current. Furthermore, the DOS depends on the dimensionality of a system, which affects SS [Fig. 1(c)]. For example, the step function of the DOS in two-dimensional (2D) systems leads us to expect steeper switching than in the corresponding three-dimensional (3D) case.[3335] This is also valid in one-dimensional (1D) systems. Thus, low-dimensional systems like 2D semiconductors or nanowires have an advantage in terms of SS in addition to electrostatic control, as expected in MOSFETs.

Kane derived a familiar equation for Zener’ s BTBT,[36] which yields the third guideline. The equation for tunneling rate G, which is proportional to I, is expressed as[32,36]

$$G = A{F^P}\exp \left( { - \frac{B}{F}} \right),$$

where A and B are Kane tunneling parameters, and P is 2 and 2.5 for direct and indirect BTBT, respectively. In the case of direct BTBT, the Kane tunneling parameters are

$$A = \frac{{gm_{\text{r}}^{1/2}{q^2}}}{{\pi {h^2}E_{\text{g}}^{1/2}}},$$
$$B = \frac{{{\pi ^2}m_{\text{r}}^{1/2}E_{\text{g}}^{3/2}}}{{qh}},$$

where g is a degeneracy factor, mr is the tunnel mass (1/mr = 1/mc +1/mv, where mc and mv are the effective masses for conduction and valence bands, respectively), and Eg is the band gap energy. According to Eqs. (3) and (5), a smaller B results in a higher tunneling current. Then, according to Eq. (5), we can expect a higher tunneling current with smaller Eg and mr. Qualitatively speaking, mc is proportional to Eg[37]; therefore, we can choose materials having both a small Eg and small mr. However, materials with a smaller effective mass have a smaller DOS.[38] Because of this trade-off relationship, a balance between Eg and mr, as expressed in Eq. (4), is required. Figure 1(d) shows a plot of G versus F calculated using Eqs. (3)(5) for typical semiconductor materials. It is noted that the OFF current in TFETs increases with decreasing Eg because of the lower tunneling barrier, although here we discuss ION and SS only.

As discussed above, the guidelines to obtain a higher tunneling current are the utilization of direct-gap semiconductors with lower Eg (so as to not increase the OFF current) and low-dimensional device structures.

Device demonstrations

To our knowledge, the best performance thus far was reported in Lund University for an N-type nanowire TFET, in which an InAs/GaAsSb heterojunction was utilized.[36] The device exhibited Ion= 10μA/μm and SS =48 mV/decade at VDS = 0.3 V. The device follows the guidelines discussed in the previous section.

Figure 2(a) shows a benchmark for experimentally demonstrated N-type TFETs. III–V TFETs exhibit higher ION values. The benchmark follows the guidelines discussed in the previous section. For Ge-TFETs, which can utilize direct tunneling, the highest performance reported thus far was achieved in Tokyo University.[37] The highest SS of 21 mV/decade was achieved in Hokkaido University with InAs/Si heterojunction nanowire TFETs.[38] For Si-TFETs, two devices showing better performance have been reported[18,51]; however, because these two devices were operated with a relatively high operation voltage, we cannot compare them with the devices shown in this benchmark.

Figure 2.

Benchmark plots for (a) N-type and (b) P-type TFETs. (c) A plot for a limited number of samples realizing integration.

Some discussions are required on P-type TFETs. Figure 2(b) shows a benchmark for P-type TFETs. Surprisingly, Si-TFETs, which are expected to show poor performance because of indirect tunneling, exhibits better performance than III-V and Ge TFETs. This is probably because it is difficult to fabricate the source-channel junction for P-type TFETs with III-V materials or Ge, for which the source is n-type and the channel is p-type. At present, we do not have a solution for this problem, but some articles discussed the feasibility of realizing P-type TFETs with these materials.[56]

Recently, some papers reported the experimental demonstration of TFET integration. Six papers reported the fabrication of both types of TFETs on the same wafer. A benchmark limited to these six papers is shown in Fig. 2(c). Of these, two papers utilized III-V TFETs,[42,43] and the other four utilized Si-TFETs.[29,48,49,58] Si-TFETs show good performance owing to the ease of integration. The guidelines for TFET development are as discussed in the previous section; however, there remain difficulties in satisfying all the guidelines.

Isoelectronic trap (IET) technology


Fortaking advantage ofthe ease ofintegrationofSi-TFETs, we aim to enhance ION in Si-TFETs sufficiently for practical application. However, the BTBT rate in Si-TFETs is low in principle. A new idea to enhance ION in Si-TFETs is to utilize a tunneling path different from BTBT, and Mori et al. proposed the use of IET technology.[27,28] The proposal is to produce an intermediate isolated state in the pn junction and utilize the tunneling current mediated by the state [Fig. 3(a)]. The intermediate state acts as a “stepping stone” for electrons tunneling from the valence to conduction bands. Thus, we can realize a tunneling path different from BTBT. In this idea, the key point is the concentration of the intermediate state. The concentration should be sufficiently low such that the intermediate state is isolated and does not form a band. In this situation, the intermediate state is not selective in terms of wave numbers, like atoms. In other words, the intermediate state can take any wave number because of the uncertainty principle. Following this scenario, we can aim to relax the k-conservation rule in indirect-gap semiconductors and realize pseudo-direct tunneling to obtain a higher tunneling rate. Here isoelectronic impurities (IEIs) are chosen to form the intermediate state. Specifically, the Al-N pair is chosen, as discussed later.

Figure 3.

(a) Schematic representation showing the idea of using intermediate states for tunneling through a pn junction. (b) Schematic atomic configuration of an Al-N pair in a host Si crystal. (c) Calculated band diagram of Si with an Al–N pair. The Al–N pair provides a discrete state in the band gap. The wave function of the discrete state at the G point is also shown.

Isoelectronic impurities

There is a long history of research on IEIs, which have been mentioned in papers published in the 1960s. IEIs are also called “isovalent electron impurities” because the impurities are isovalent with the host material and do not produce carriers. In the simplest substitutional view, for Si, other group-IV elements such as C, Ge, and Sn can be IEIs. The impurity pairs following the octet rule, such as III–V and II–VI pairs, are also IEIs if they do not produce dangling bonds. The definition as not producing carriers is notably wide, but the IEIs of interest form states in the band gap of host materials and produce unique physical phenomena such as luminescence. The mechanisms for the formation of states by IEIs have been discussed previously.[59] There are two scenarios: one is that the core charge, different from that of the host material, provides strong short-range potential perturbation, while the other is that the atom-size difference between the IEIs produces local strains resulting in potential perturbation in the host material.

Thus far, the most successful application of IEIs has been green light-emitting diodes (LEDs) realized using GaP:N before the InGaN era. GaP is an indirect-gap host material.[60] The IEI in this application is N, which forms N–N pairs in the host GaP and realizes strong pseudo-direct luminescence at room temperature. Specifically, the luminescence originates from the exciton emission bound to the IET.

Isoelectronic impurities in silicon

The IEIs in Si have also been studied with the motivation to realize LEDs. Unfortunately, the binding energy of excitons bound to IET states is not sufficient for emission at room temperature, because of which its practical application has not been realized yet. The situation of IETs in Si is slightly complicated. The substitutional C, Ge, and Sn—the previously called “simple” IEIs—do not exhibit the exciton emission bound to the IETs. It is supposed that these IEIs do not yield the important states in the band gap. The IET emissions were observed with single-atom IEIs, which are In,[61] Be,[62] Cu,[63] S,[64] Se,[65] and Zn,[66] and an atom-pair IEI, which is Al-N.[67] The single-atom IEIs contain donor/acceptor impurities. For Zn, for example, it is suggested that Zn-O pairs are produced with residual O impurities in Si substrates.[68] For Be, the IET is produced by Be-Be pairs.[69] For In, it is suggested that residual N atoms in Si substrates cause the IET formation.[59]

There are a relatively large number of papers on the Al-N IEI, and we utilized the Al-N IEI for our works. First, Weber et al. experimentally investigated emissions observed in Si:Al in detail; then, they suggested that the IETs in Si:Al were produced by a substitutional pair having C3v symmetry along the (111) axis.[70] Subsequently, Alt and Tapfer revealed that N atoms participate in these emissions,[71] and Modavis and Hall realized strong luminescence by the co-doping of Al and N.[67] Moreover, Tajima and Kamata utilized these emissions to estimate the residual N concentration in Si wafers.[72] The IET state is approximately 30 meV below the CBM.[70] The most recent studies were conducted by Iizuka and Nakayama using first-principles calculations.[73,74] They clarified the stable atomic configuration of the Al-N pair: the substitutional nearest-neighbor configuration is preferred over configurations comprising interstitials [Fig. 3(b)]. This configuration follows the prediction of Weber et al. based on their experiments. The Al-N pair provides a state in the band gap, which mainly comprises the N 3s state [Fig. 3(c)].[73]

Proof-of-concept experiments

On diodes

In this section, we discuss the enhancement of tunneling current flowing in diodes under the reverse-bias condition resulting from the introduction of an IEI, which was the first proof-of-concept experiment.[27,28] The diode consisted of an n-type epitaxial Si thin film on a p-type substrate [Fig. 4(a)]. The Al-N IEI was doped by the ion implantation (I/I) processes and activated by low-temperature annealing at 450°C. The formation of the IET state was confirmed by photoluminescence spectroscopy at cryogenic temperature. The concentrations of Al and N were approximately 1018 cm−3 around the pn junction. Four types of diodes were examined: Al–N-, Al-, and N-implanted diodes and a control diode without additional impurities [Fig. 4(b)]. The temperature dependence of tunneling current in the control diode follows the trend of conventional indirect BTBT.[28] In the higher temperature range, the tunneling current flowing in the implanted diodes comprises the so-called trap-assisted tunneling (TAT) consisting of tunneling to an impurity or defect state and thermal emission from the state to the band. Therefore, it is fair to compare such currents with currents in the lower temperature range, in which tunneling consists of “pure” tunneling without thermal paths. In the comparison, the Al–N-implanted diode exhibited a current enhancement by a factor of 735, which implies that the Al–N co-doping enhances the tunneling current. The Al-implanted diode also exhibited current enhancement, but the enhancement was less than that in the Al–N case and is probably similar to the case of Tajima’s experiments,[72] in which the residual N impurity in a Si wafer causes the Al–N formation. The N-implanted diode exhibited no enhancement, but the current decreased because I/I defects are likely to compensate for carrier-generating dopants making the junction less steep. The current enhancement does not originate from the change of carrier concentration accompanying Al and N doping. The co-doping of Al and N induces hole generation in Si, and its activation ratio is approximately 10%.[75] Therefore, the change of carrier concentration does not significantly affect tunneling current.

Figure 4.

(a) Schematic representation of diodes fabricated in Refs. 27 and 28. (b) Temperature dependence of four types of diodes.[28] (c) Summary of tunneling paths in IET-assisted diodes.[28]

The above experiment was the first to show that the co-doping of Al and N enhances the tunneling current in Si. The supposed tunneling paths are summarized in Fig. 4(c). From this demonstration, it is not certain what IETT is—it will be discussed later with the results of a theoretical calculation.


The next experiment was on TFETs,[27,76] which demonstrated N-type TFETs on a silicon-on-insulator (SOI) wafer. The high-k/metal gate technology was also utilized [Fig. 5(a)]. The I–V characteristics at room temperature are shown in Fig. 5(b). The IdVd curves exhibit ION enhancement by a factor of 11 owing to the doping of Al–N. The SS was also improved owing to the current enhancement, as expected from Eq. (3). These improvements were also observed at a cryogenic temperature, as in the diode case. The IOFF slightly increased because of the increase of tunneling current flowing through the junction at the drain side. This is not essential for the IET technology. If we utilize the so-called drain-offset structure,[77] we can avoid the IOFF increase despite utilizing IET technology.[78] Unfortunately, the enhancement is less than that of diodes, which is supposed to be related to the mechanism of IETT, as discussed later. The entire active region consisting of the source, channel, and drain was exposed by Al-N I/I in the experiments. Then, the source sheet resistance was increased with I/I,[27] which suggests that Al-N implantations compensate for carrier-generating dopants, as is the case with N implantation in the diodes.

Figure 5.

(a) Schematic representation of an N-type TFET fabricated on an SOI wafer.[27] (b) I - V curves of the control TFET, which does not incorporate IET, and IET-TFET.[27]

Another experiment has been conducted utilizing heated ion implantation (HII),[78] which is used to reduce implantation defects by heating the wafer when I/I is performed. In the experiment, the wafer was heated to 200°C in the Al and N implantation processes. The HII process realized an ION value three times that of the conventional IET-TFET with the RT I/I process. A lower number of I/I defects result in stronger IET effects. The comprehensive scenario is as follows. The defects hamper the IET activation. Fewer defects increase active IET and result in the greater current enhancement. It is supposed that the current enhancement with IET notably concerns the microscopic structure surrounding Al-N pairs.

On TFET circuits

The final objective of ION enhancement is faster circuit operation. Complementary TFET (CTFET) circuit operation has been demonstrated with the IET technology.[29] The experiment was slightly different from the experiments in the previous section. ION enhancement by factors of five and two has been achieved in P- and N-type TFETs, respectively [Fig. 6(a)].

Figure 6.

(a) IDVD curves of P- and N-type TFETs. The IET technology enhances tunneling current.[29] (b) SEM image, schematic structure, and transfer curves of TFET inverters.[29] (c) Optical microscope image, schematic circuit diagram, and output waveforms of 23-stage full TFET ring oscillators.[29]

The simplest CTFET circuit is an inverter, as shown in Fig. 6(b). A higher gain was achieved, especially in a low operationvoltage range, owing to the ION enhancement. The full swing was not achieved because of the high IOFF, which can be avoided by using the drain-offset structure simulated as an orange curve in Fig. 6(b). The situation seems to be the case in the previous section.

The ring oscillator (RO) circuit is fabricated to estimate circuit operation speed, which is the first performance indicator for newly developed devices. Twenty-three-stage full TFET ROs, in which all transistors were TFETs, were fabricated and successfully operated [Fig. 6(c)].[27] The output waveforms are also shown in the figure. It is clear that the IET technology enhances operation speed owing to the current enhancement. It is noted that this was the first demonstration of RO circuit operation for TFETs.

Theoretical view of IETT

Iizuka et al. reported the theoretical framework of IETT.[79] This section is based on their paper. Figure 7(a) shows the tunneling path of IETT. Electron tunneling occurs in path A, which has a long distance. It is assumed that electrons move in path B by drift transport because the IET state resonates with the CB state. We find that the assumption is correct later. It is noted that IETT does not include thermal paths; therefore, it is expected that IETT exhibits no temperature dependence like TAT, which includes a thermal transition path. On the other hand, the experiments showed a temperature dependence of SS. It was probably caused by TAT originating from defects in the junction, which are not an essential characteristic of IETT.[27]

Figure 7.

(a) Tunneling of IETT consisting of two paths: the longer path A and the shorter path B. (b) Plot of components of ?IET decomposed by wave functions of host Si, ?Si,µ, as a function of eigenenergy, where


2 =



2.[79] (c) Tunneling probability of BTBT and IETT. The length of path B is assumed as d = 1 nm.[79] ‘

According to Eq. (1), we should first consider DOS. The DOS of the VBM and CBM were estimated as Dv= 1.19 × 1010 eV−1 and Dc = 8.16 × 109 eV−1, respectively. In contrast, the DOS of the IET state was liberally estimated as DIET = 3.25 × 107eV−1 under the assumption that all Al and N atoms formed activated pairs in the host material. As DIET is two orders of magnitude less than Dc,|M|2 must compensate for the shortage to realize a higher current.

Two factors are involved in the enhancement of |M|2. One is tunneling length. The effective tunneling length of IETT is the length of path A shown in Fig. 7(a), which is clearly shorter than the length of BTBT, resulting in a larger |M|2. Here, we consider path B in which electrons move by drift transport as assumed in the first part of this section. Figure 7(b) shows a plot of components of ψIET decomposed by the wave functions of host Si as a function of eigenenergy. The IET state mainly comprises X-point-like states. This indicates that the IET state resonates with the CBM state of host Si, because of which path B does not contribute to tunneling and IETT takes advantage of the shorter tunneling length. The other factor is the relaxed k-conservation rule. Figure 7(b) also shows that the variety of components is notably significant, which indicates that the IET state is localized and can relax the k-conservation rule along the tunneling direction. In relation to this, it is also important that the probability of BTBT in silicon is lower because of p-to-p transition as discussed previously, while the probability of IETT is higher because of p-to-s transition owing to the N-3s orbital nature of the IET state as discussed with Fig. 3(c). These two factors, tunneling length and relaxed k-conservation rule, enhance |M|2 to enhance tunneling current, despite the lower DOS.

Figure 7(c) shows the tunneling probability as a function of tunneling length. Both BTBT and IETT show the same trend of exponential increase with decreasing length. Here, we point out the difference of slope between these two curves. This difference is due to the difference of envelope function, and it indicates that a shorter tunneling length can realize a much higher enhancement ratio between IETT and BTBT. That is, ifwe realize a much shorter tunneling length—through device-structure modification, for example—we can expect a higher ION in Si-TFETs. Furthermore, it is speculated that this causes the difference of enhancement ratio between the diodes and TFETs in the experiments. This fact is notably promising for Si-TFETs because we can expect a higher ION than in the proof-of-concept experiments.

Summary and future outlook

In summary, we reviewed the IET technology proposed to enhance ION in Si-TFETs. The proof-of-concept experiments demonstrated an ION enhancement in SOI-TFETs by a factor of approximately 10. Theoretical calculation predicts that it is possible to realize a much higher ION enhancement.

Here we comment on certain features of TFETs not mentioned in the main text. The fabrication process of Si-TFETs is compatible with that of conventional Si-MOSFETs; therefore, the fabrication cost does not matter. The scalability is expected to be better than that of MOSFETs because the short-channel effect is supposed to be insignificant in TFETs, the major characteristics of which are determined by the source-side edge of the gate. Therefore, in principle, planar-type TFETs could operate even in the technology node in which finFETs are utilized. The most important issue in the fabrication is source/drain formation because the self-alignment process of the source and drain for TFETs is not clear at present, which could hamper dimensional scaling. The performance variability is also under research. Especially for IET-TFETs, we can speculate that the IET impurities provide additional variation. On the other hand, it was reported that IET-TFETs exhibited less variation than conventional TFETs in the case of large devices, which is attributed to the decrease of tunneling rate fluctuation with the increase of tunneling probability.[76] Smaller IET-TFETs could exhibit much larger variation because of impurity fluctuation; however, there is a trade-off relationship between the increase of impurity fluctuation and the suppression of tunneling rate fluctuation. More research is needed to discuss the variability of IET-TFETs in detail.

Finally, we present an estimation of the future performance of IET-TFETs by utilizing simulations.[29] The enhancement in Si-TFET was assumed to be as high as in the case of the diodes; that is, enhancement by a factor of 735 was assumed. Here, not only ION enhancement but also threshold-voltage optimization and device miniaturization to reduce capacitance were considered. The target operation voltage is approximately 0.3 V, at which MOSFETs show subthreshold operation.[80] Here, MOSFETs operate with diffusion current, because of which mobility enhancement technologies to enhance drift current cannot be utilized. In this low operation-voltage range, IET-TFETs can be comparable or superior to 65-nm-node MOSFETs.

A similar prediction has been reported for III-VorGe TFETs. These TFETs still have issues as P-type TFETs and in the device integration process. On the other hand, IET-TFETs are required to realize a much higher ION experimentally. Now, we have some types of TFETs as candidates for building blocks oflow-power-consumptionLSIs. Competitionfordevice demonstrations with performance suitable for practical application is underway. At present, it is not certain which TFET is the best, but researchers are expected to usher in a new era of highperformance computers realized by new low-power-consumption transistors.


  1. 1.

    G.E. Moore: Cramming more components onto integrated circuits. Electronics 38, 114 (1965).

    Google Scholar 

  2. 2.

    G.E. Moore: Progress in digital integrated electronics. In Technical Digest IEEE Int. Electron Devices Meeting, 1975, pp. 11–13.

    Google Scholar 

  3. 3.

    J.G. Koomey, S. Berard, M. Sanchez, and H. Wong: Implications of historical trends in the electrical efficiency of computing. IEEE Ann. Hist. Comput. 33, 46 (2011).

    Article  Google Scholar 

  4. 4.

    R.H. Dennard, F.H. Gaensslen, V.L. Rideout, E. Bassous, and A.R. LeBlanc: Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE J. Solid-State Circuits 9, 256 (1974).

    Article  Google Scholar 

  5. 5.

    Y. Taur and T.H. Ning: Fundamentals of Modern VLSI Devices, 2nd ed. (Cambridge Univ. Press, Cambridge, England, 2009), p. 175.

    Book  Google Scholar 

  6. 6.

    D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Fu: FinFET—a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans. Electron Devices 47, 2320 (2000).

    CAS  Article  Google Scholar 

  7. 7.

    K.J. Kuhn: Considerations for ultimate CMOS scaling. IEEE Trans. Electron Devices 59, 1813 (2012).

    CAS  Article  Google Scholar 

  8. 8.

    J. Robertson: High dielectric constant gate oxides for metal oxide Si transistors. Rep. Prog. Phys. 69, 327 (2006).

    CAS  Article  Google Scholar 

  9. 9.

    S.M. Sze: Physics of Semiconductor Devices, 2nd ed. (Wiley-Interscience Publication, New York, USA, 1981), p. 446.

    Google Scholar 

  10. 10.

    A.C. Seabaugh and Q. Zhang: Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE 98, 2095 (2010).

    CAS  Article  Google Scholar 

  11. 11.

    S. Salahuddin and S. Datta: Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett. 8, 405 (2008).

    CAS  Article  Google Scholar 

  12. 12.

    N. Shukla, B. Grisafe, R.K. Ghosh, N. Jao, A. Aziz, J. Frougier, M. Jerry, S. Sonde, S. Rouvimov, T. Orlova, S. Gupta, and S. Datta: Ag/HfO2 based threshold switch with extreme non-linearity for unipolar cross-point memory and steep-slope phase-FETs. In Technical Digest IEEE Int. Electron Devices Meeting, 2016, pp. 866–869.

    Google Scholar 

  13. 13.

    O.M. Stuetzer: Junction fieldistors. Proc. IRE 40, 1377 (1952).

    Article  Google Scholar 

  14. 14.

    W. Schockley and W.W. Hopper: The surface controlled avalanche transistor. In Proc. WESCON, vol. 64, 1964, p. 12.1.

    Google Scholar 

  15. 15.

    J.J. Quinn, G. Kawamoto, and B.C. McCombe: Subband spectroscopy by surface channel tunneling. Surf. Sci. 73, 190 (1978).

    CAS  Article  Google Scholar 

  16. 16.

    T. Baba: Proposal for surface tunnel transistors. Jpn. J. Appl. Phys. 31, L455 (1992).

    CAS  Article  Google Scholar 

  17. 17.

    J. Appenzeller, Y.-M. Lin, J. Knoch, and P. Avouris: Band-to-band tunneling in carbon nanotube field-effect transistors. Phys. Rev. Lett. 93, 196805 (2004).

    CAS  Article  Google Scholar 

  18. 18.

    W.Y. Choi, B.-G. Park, J.D. Lee, and T.-J. King Liu: Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28, 743 (2007).

    CAS  Article  Google Scholar 

  19. 19.

    S.H. Kim, H. Kam, C. Hu, and T.-J. King Liu: Germanium-source tunnel field effect transistors with record high ION/IOFF. In Symp. VLSI Technology–Digest of Technical Papers, 2009, p. 178.

    Google Scholar 

  20. 20.

    F. Mayer, C. Le Royer, J.-F. Damlencourt, K. Romanjek, F. Andrieu, C. Tabone, B. Previtali, and S. Deleonibus: Impact of SOI, Si1−xGexOI and GeOI substrates on CMOS compatible tunnel FET performance. In Technical Digest IEEE Int. Electron Devices Meeting, 2008, p. 163.

    Google Scholar 

  21. 21.

    Q. Huang, Z. Zhan, R. Huang, X. Mao, L. Zhang, Y. Qiu, and Y. Wang: Si tunnel transistors with a novel silicided source and 46 mV/dec swing. In Technical Digest IEEE Int. Electron Devices Meeting, 2001, p. 382.

    Google Scholar 

  22. 22.

    K. Jeon, W.-Y. Loh, P. Patel, C.Y. Kang, J. Oh, A. Bowonder, C. Park, C.S. Park, C. Smith, P. Majhi, H.-H. Tseng, R. Jammy, T.-J. King Liu, and C. Hu: Si tunnel transistors with a novel silicided source and 46 mV/dec swing. In Symp. VLSI Technology–Digest of Technical Papers, 2010, p. 121.

    Google Scholar 

  23. 23.

    R. Gandhi, Z. Chen, N. Singh, K. Banerjee, and S. Lee: Vertical Si-nanowire n-type tunneling FETs with low subthreshold swing (≤50 mV/decade) at room temperature. IEEE Electron Device Lett. 32, 437 (2011).

    CAS  Article  Google Scholar 

  24. 24.

    T. Mori, T. Yasuda, K. Fukuda, Y. Morita, S. Migita, A. Tanabe, T. Maeda, W. Mizubayashi, S. O’uchi, Y. Liu, M. Masahara, N. Miyata, and H. Ota: Unexpected equivalent-oxide-thickness dependence of the subthreshold swing in tunnel field-effect transistors. Appl. Phys. Express 7, 024201 (2014).

    Article  CAS  Google Scholar 

  25. 25.

    S. Takagi, D.H. Ahn, M. Noguchi, T. Gotow, K. Nishi, M. Kim, and M. Takenaka: Tunneling MOSFET technologies using III–V/Ge materials. In Technical Digest IEEE Int. Electron Devices Meeting, 2016, pp. 516–519.

    Google Scholar 

  26. 26.

    M. Li, R. Yan, D. Jena, and H.G. Xing: Two-dimensional heterojunction interlayer tunnel FET (Thin-TFET): from theory to applications. In Technical Digeast IEEE Int. Electron Devices Meeting, 2016, pp. 504–507.

    Google Scholar 

  27. 27.

    T. Mori, Y. Morita, N. Miyata, S. Migita, K. Fukuda, M. Masahara, T. Yasuda, and H. Ota: Band-to-band tunneling current enhancement utilizing isoelectronic trap and its application to TFETs. In Symp. VLSI Technology–Digest of Technical Papers, 2014, pp. 86–87.

    Google Scholar 

  28. 28.

    T. Mori, Y. Morita, N. Miyata, S. Migita, K. Fukuda, W. Mizubayashi, M. Masahara, T. Yasuda, and H. Ota: Study of tunneling transport in Si-based tunnel field-effect transistors with ON current enhancement utilizing isoelectronic trap. Appl. Phys. Lett. 106, 083501 (2015).

    Article  CAS  Google Scholar 

  29. 29.

    T. Mori, H. Asai, J. Hattori, K. Fukuda, S. Otsuka, Y. Morita, S. O’uchi, H. Fuketa, S. Migita, W. Mizubayashi, H. Ota, and T. Matsukawa: Demonstrating performance improvement of complementary TFET circuits by ION enhancement based on isoelectronic trap technology. In Technical Digeast IEEE Int. Electron Devices Meeting, 2016, pp. 512–515.

    Google Scholar 

  30. 30.

    A.M. Ionescu and H. Riel: Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329 (2011).

    CAS  Article  Google Scholar 

  31. 31.

    S. Datta: Electronic Transport in Mesoscopic Systems (Cambridge University Press, Cambridge, England, 1995), p. 161.

    Book  Google Scholar 

  32. 32.

    K.-H. Kao, A.S. Verhulst, W.G. Vandenberghe, B. Sorée, G. Groeseneken, and K. De Meyer: Direct and indirect band-to-band tunneling in Germanium-based TFETs. IEEE Trans. Electron. Devices 59, 292 (2012).

    CAS  Article  Google Scholar 

  33. 33.

    L. Lattanzio, L. De Michielis, and A.M. Ionescu: The electron-hole bilayer tunnel FET. Solid-State Electron. 74, 85 (2012).

    CAS  Article  Google Scholar 

  34. 34.

    C. Alper, L. Lattanzio, L. De Michielis, P. Palestri, L. Selmi, and A.M. Ionescu: Quantum mechanical study of the Germanium electron-hole bilayer tunnel FET. IEEE Trans. Electron. Devices 60, 2754 (2013).

    Article  Google Scholar 

  35. 35.

    S. Agarwal, J.T. Teherani, J.L. Hoyt, D.A. Antoniadis, and E. Yablonovitch: Engineering the electron-hole bilayer tunneling field-effect transistor. IEEE Trans. Electron. Devices 61, 1599 (2014).

    CAS  Article  Google Scholar 

  36. 36.

    E.O. Kane: Zener tunneling in semiconductors. J. Phys. Chem. Solids 12, 181 (1960).

    CAS  Article  Google Scholar 

  37. 37.

    W.A. Harrison: Electronic Structure and the Properties of Solids (Dover Publications, New York, USA, 1989), p. 158.

    Google Scholar 

  38. 38.

    J.H. Davis: The Physics of Low-dimensional Semiconductors (Cambridge University Press, Cambridge, England, 1998), p. 26.

    Google Scholar 

  39. 39.

    E. Memisevic, J. Svensson, M. Hellenbrand, E. Lind, and L.-E. Wernersson: Vertical InAs/GaAsSb/GaSb tunneling field-effect transistor on Si with S=48 mV/decade and Ion=10 µA/μm for Ioff=1 nA/μm at VDS=0.3 V. In Technical Digeast IEEE Int. Electron Devices Meeting, 2016, pp. 500–503.

    Google Scholar 

  40. 40.

    M. Kim, Y. Wakabayashi, R. Nakane, M. Yokoyama, M. Takenaka, and S. Takagi: High Ion/Ioff Ge-source ultrathin body strained-SOI tunnel FETs. In Technical Digest IEEE Electron Devices Meeting, 2014, pp. 331–334.

    Google Scholar 

  41. 41.

    K. Tomioka, M. Yoshimura, and T. Fukui: Steep-slope tunnel field-effect transistors using III-V nanowire/Si heterojunction. In Symp. VLSI Technology–Digest of Technical Papers, 2012, pp. 47–48.

    Google Scholar 

  42. 42.

    R. Pandey, H. Madan, H. Liu, V. Chobpattana, M. Barth, B. Rajamohanan, M.J. Hollander, T. Clark, K. Wang, J.-H. Kim, D. Gundlach, K.P. Cheung, J. Suehle, R. Engel-Herbert, S. Stemmer, and S. Datta: Demonstration of p-type In0.7Ga0.3As/GaAs0.35Sb0.65 and n-type GaAs0.4Sb0.6/In0.65Ga0.35As complimentary heterojunction vertical tunnel FETs for ultra-low power logic. In Symp. VLSI Technology–Digest of Technical Papers, 2015, pp. 206–207.

    Google Scholar 

  43. 43.

    D. Cutaia, K.E. Moselund, H. Schmid, M. Borg, A. Olziersky, and H. Riel: Complementary III-V heterojunction lateral NW tunnel FET technology on Si. In Symp. VLSI Technology–Digest Technical Papers, 2016, pp. 226–227.

    Google Scholar 

  44. 44.

    D.H. Ahn, S.M. Ji, M. Takenaka, and S. Takagi: Performance improvement of InxGa1-xAs tunnel FETs with quantum well and EOT scaling. In Symp. VLSI Technology–Digest of Technical Papers, 2016, pp. 224–225.

    Google Scholar 

  45. 45.

    M. Noguchi, S.H. Kim, M. Yokoyama, S.M. Ji, O. Ichikawa, T. Osada, M. Hata, M. Takenaka, and S. Takagi: High Ion/Ioff and low subthreshold slope planar-type InGaAs Tunnel FETs with Zn-diffused source junctions. In Technical Digest. IEEE Int. Electron Devices Meeting, 2013, pp. 683–686.

    Google Scholar 

  46. 46.

    D.K. Mohata, R. Bijesh, Y. Zhu, M.K. Hudait, R. Southwick, Z. Chbili, D. Gundlach, J. Suehle, J.M. Fastenau, D. Loubychev, A.K. Liu, T.S. Mayer, V. Narayanan, and S. Datta: Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio. In Symp. VLSI Technology–Digest of Technical Papers, 2012, pp. 53–54.

    Google Scholar 

  47. 47.

    T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat: Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and <60 mV/dec subthreshold slope. In Technical Digest IEEE Int. Electron Devices Meeting, 2008, pp. 947–949.

    Google Scholar 

  48. 48.

    Q. Huang, R. Jia, C. Chen, H. Zhu, L. Guo, J. Wang, J. Wang, C. Wu, R. Wang, W. Bu, J. Kang, W. Wang, H. Wu, S.-W. Lee, Y. Wang, and R. Huang: First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: manufacturability, variability and technology roadmap. In Technical Digest IEEE Int. Electron Devices Meeting, 2015, pp. 604–607.

    Google Scholar 

  49. 49.

    Y. Kondo, M. Goto, Y. Morita, T. Mori, S. Migita, A. Hokazono, H. Ota, M. Masahara, and S. Kawanaka: Novel device architecture proposal of source junctionless tunneling field-effect transistor (SJL-TFET). In Ext. Abst. Int. Conf. Solid State Devices and Materials, 2014, pp. 826–827.

    Google Scholar 

  50. 50.

    Q. Huang, R. Huang, Z. Zhan, Y. Qiu, W. Jiang, C. Wu, and Y. Wang: A novel Si tunnel FET with 36 mV/dec subthreshold slope based on junction depleted-modulation through striped gate configuration. In Technical Digest IEEE Int. Electron Devices Meeting, 2012, pp. 187–190.

    Google Scholar 

  51. 51.

    Q. Huang, Z. Zhan, R. Huang, X. Mao, L. Zhang, Y. Qiu, and Y. Wang: Self-depleted T-gate Schottky barrier tunneling FET with low average subthreshold Slope and high ION/IOFF by gate configuration and barrier modulation. In Technical Digest IEEE Int. Electron Devices Meeting, 2011, pp. 382–385.

    Google Scholar 

  52. 52.

    R. Gandhi, Z. Chen, N. Singh, K. Banerjee, and S. Lee: Vertical Si-Nanowire n-Type tunneling FETs with low subthreshold swing (≤50 mV/decade) at room temperature. IEEE Electron Devices Lett. 32, 437 (2011).

    CAS  Article  Google Scholar 

  53. 53.

    S.H. Kim, H. Kam, C. Hu, and T.-J. King Liu: Germanium-source tunnel field effect transistors with record ION/IOFF. In Symp. VLSI Technology Digest Technical Papers, 2009, pp. 178–179.

    Google Scholar 

  54. 54.

    K. Jeon, W.-Y. Loh, P. Patel, C.Y. Kang, J. Oh, A. Bowonder, C. Park, C.S. Park, C. Smith, P. Majhi, H.-H. Tseng, R. Jammy, T.-J. King Liu, and C. Hu: Si tunnel transistors with a novel silicided source and 46 mV/dec swing. In Symp. VLSI Technology Digest Technical Papers, 2010, pp. 121–122.

    Google Scholar 

  55. 55.

    F. Mayer, C. Le Royer, J.-F. Damlencourt, K. Romanjek, F. Andrieu, C. Tabone, B. Previtali, and S. Deleonibus: Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible tunnel FET performance. In Technical Digest IEEE Int. Electron Devices Meeting, 2008, pp. 163–166.

    Google Scholar 

  56. 56.

    R. Pandey, C. Schulte-Braucks, R.N. Sajjad, M. Barth, R.K. Ghosh, B. Grisafe, P. Sharma, N. von den Driesch, A. Vohra, B. Rayner, R. Loo, S. Mantl, D. Buca, C.-C. Yeh, C.-H. Wu, W. Tsai, D. Antoniadis, and S. Datta: Performance benchmarking of p-type In0.65Ga0.35As/GaAs0.4Sb0.6 and Ge/Ge0.93Sn0.07 hetero-junction tunnel FETs. In Technical Digest Int. Electron Devices Meeting, 2016, pp. 520–523.

    Google Scholar 

  57. 57.

    S. Blaeser, S. Glass, C. Schulte-Braucks, K. Narimani, N.V.D. Driesch, S. Wirths, A.T. Tiedemann, S. Trellenkamp, D. Buca, Q.T. Zhao, and S. Mantl: Novel SiGe/Si line tunneling TFET with high Ion at low VDD and constant SS. In Technical Digest Int. Electron Devices Meeting, 2015, pp. 608–611.

    Google Scholar 

  58. 58.

    Y. Morita, T. Mori, S. Migita, W. Mizubayashi, K. Fukuda, T. Matsukawa, K. Endo, S. O’uchi, Y. Liu, M. Masahara, and H. Ota: Improvement of epitaxial channel quality on heavily arsenic- and boron-doped Si surfaces and impact on performance of tunnel field-effect transistors. Solid-State Electron. 113, 173 (2015).

    CAS  Article  Google Scholar 

  59. 59.

    T.G. Brown and D.G. Hall: Radiative isoelectronic impurities in silicon and silicon-germanium alloys and superlattices, in light emission in silicon. In Semiconductors and Semimetals, edited by D.J. Lockwood (Academic Press, 49, San Diego, USA, 1998), p. 79.

    Google Scholar 

  60. 60.

    D.G. Thomas and J.J. Hopfield: Isoelectronic traps due to nitrogen in gallium phosphide. Phys. Rev. 150, 680 (1966).

    CAS  Article  Google Scholar 

  61. 61.

    M.L.W. Thewalt, U.O. Ziemelis, and R.R. Parsons: Enhancement of long lifetime lines in photoluminescence from Si. Solid State Commun. 39, 27 (1981).

    CAS  Article  Google Scholar 

  62. 62.

    M.O. Henry, E.C. Lightowlers, N. Killoran, D.J. Dunstan, and B.C. Cavenett: Bound exciton recombination in beryllium-doped silicon. J. Phys. C: Solid State Phys. 14, L255 (1981).

    CAS  Article  Google Scholar 

  63. 63.

    J. Weber, H. Bauch, and R. Sauer: Optical properties of copper in silicon: excitons bound to isoelectronic copper pairs. Phys. Rev. B 25, 7688 (1982).

    CAS  Article  Google Scholar 

  64. 64.

    T.G. Brown and D.G. Hall: Optical emission at 1.32 µm from sulfur-doped crystalline silicon. Appl. Phys. Lett. 49, 245 (1986).

    CAS  Article  Google Scholar 

  65. 65.

    P.L. Bradfield, T.G. Brown, and D.G. Hall: Radiative decay of excitons bound to chalcogen-related isoelctronic impurity complexes in silicon. Phys. Rev. B 38, 3533 (1988).

    CAS  Article  Google Scholar 

  66. 66.

    M.O. Henry, J.D. Campion, and K.G. McGuigan: A photoluminescence study of zinc-implanted silicon. Mat. Sci. Eng. B 4, 201 (1989).

    Article  Google Scholar 

  67. 67.

    R.A. Modavis and D.G. Hall: Aluminum–nitrogen isoelectronic trap in silicon. J. Appl. Phys. 67, 545 (1990).

    CAS  Article  Google Scholar 

  68. 68.

    S.E. Daly, E. McGlynn, M.O. Henry, J.D. Campion, K.G. McGuigan, M.C. do Carmo, and M.H. Nazaré: The complexing of oxygen with the group II impurities Be, Cd, and Zn in silicon. Mater. Sci. Eng. B 36, 116 (1996).

    Article  Google Scholar 

  69. 69.

    T.G. Brown, P.L. Bradfield, D.G. Hall, and R.A. Soref: Optical emission from impurities within an epitaxial-silicon optical waveguide. Opt. Lett. 12, 753 (1987).

    CAS  Article  Google Scholar 

  70. 70.

    J. Weber, W. Schmid, and R. Sauer: Localized exciton bound to an isoelectronic trap in silicon. Phys. Rev. B 21, 2401 (1980).

    CAS  Article  Google Scholar 

  71. 71.

    H. Ch. Alt and L. Tapfer: Photoluminescence study of nitrogen implanted silicon. Appl. Phys. Lett. 45, 426 (1984).

    CAS  Article  Google Scholar 

  72. 72.

    M. Tajima and Y. Kamata: Quantification of nitrogen in silicon by luminescence activation using aluminum ion implantation. Jpn. J. Appl. Phys. 52, 086602 (2013).

    Article  CAS  Google Scholar 

  73. 73.

    S. Iizuka and T. Nakayama: First-principles calculation of electronic properties of isoelectronic impurity complexes in Si. Appl. Phys. Express 8, 081301 (2015).

    Article  CAS  Google Scholar 

  74. 74.

    S. Iizuka and T. Nakayama: Stability and electronic structure of isoelectronic impurity complexes in Si: first-principles study. Jpn. J. Appl. Phys. 55, 101301 (2016).

    Article  CAS  Google Scholar 

  75. 75.

    T. Mori et al., to be presented elsewhere.

  76. 76.

    T. Mori, S. Migita, K. Fukuda, H. Asai, Y. Morita, W. Mizubayashi, Y. Liu, S. O’uchi, H. Fuketa, S. Otsuka, T. Yasuda, M. Masahara, H. Ota, and T. Matsukawa: Suppression of tunneling rate fluctuations in tunnel field-effect transistors by enhancing tunneling probability. Jpn. J. Appl. Phys. 56, 04CD02 (2017).

    Article  Google Scholar 

  77. 77.

    T. Mori, T. Yasuda, T. Maeda, W. Mizubayashi, S. O’uchi, Y. Liu, K. Sakamoto, M. Masahara, and H. Ota: Tunnel field-effect transistors with extremely low off-current using shadowing effect in drain implantation. Jpn. J. Appl. Phys. 50, 06GF14 (2011).

    Article  Google Scholar 

  78. 78.

    T. Mori, W. Mizubayashi, Y. Morita, S. Migita, K. Fukuda, N. Miyata, T. Yasuda, M. Masahara, and H. Ota: Effect of hot implantation on ON-current enhancement utilizing isoelectronic trap in Si-based tunnel field-effect transistors. Appl. Phys. Express 8, 036503 (2015).

    CAS  Article  Google Scholar 

  79. 79.

    S. Iizuka, Y. Asayama, and T. Nakayama: Tunneling current characteristics by Al+N isoelectronic traps in Si-TFET; first-principles study. Mater. Sci. Semicond. Process., to be published.

  80. 80.

    J. Myers, A. Savanth, D. Howard, R. Gaddh, P. Prabhat, and D. Flynn: An 80 nm retention 11.7 pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65 nm CMOS for WSN applications. In Technical Digest IEEE Int. Solid-State Circuits Conf., 2015, pp. 144–145.

    Google Scholar 

Download references


This study was supported by the FIRST program initiated by CSTP through JSPS, JSPS KAKENHI Grant-in-Aid for Young Scientists (A) No. 15H05526, and NEDO, Japan.

Author information



Corresponding author

Correspondence to Takahiro Mori.

Rights and permissions

This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if changes were made. The images or other third party material in this article are included in the article's Creative Commons licence, unless indicated otherwise in a credit line to the material. If material is not included in the article's Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this licence, visit

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Mori, T., Iizuka, S. & Nakayama, T. Material engineering for silicon tunnel field-effect transistors: isoelectronic trap technology. MRS Communications 7, 541–550 (2017).

Download citation