Two causes of source/drain series resistance in bottom-contact pentacene thin-film transistors

MRS Online Proceedings Library volume 814, pages225–230(2004)Cite this article

Abstract

We identified two causes of source/drain (S/D) series resistance (Rs) in bottom-contact (BC) pentancene thin-film transistors (TFTs). One is mixed-phase pentacene grown in the blurred- edge region of Au electrodes and the other is the semi-insulating pentacene region between the Au electrode and the carrier-accumulating layer. A novel Au S/D electrode structure with a self-assembled monolayer (SAM) adhesion layer enables direct injection of carriers into the accumulating layer and markedly reduces Rs for unit gate width (RsW) to 6 MΩ µm. BC TFTs with this electrode structure showed extrinsic field-effect mobility as high as 1.1 cm2/Vs.

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Acknowledgments

We would like to thank Drs. K. Tsukakoshi and I. Yagi for valuable discussions, Mr. N. Kimura for experimental supports, and Mr. S. Tanaka for a providing FIB-SIM image.

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Affiliations

  1. Fusion Domain Laboratory, Sony Corporation, Higashikojiya Ota-ku, Tokyo, 144-0033, Japan

    Makoto Noda, Nobuhide Yoneya, Nobukazu Hirai, Noriyuki Kawashima, Kazumasa Nomoto, Masaru Wada & Jiro Kasahara

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  1. Makoto Noda
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  2. Nobuhide Yoneya
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  3. Nobukazu Hirai
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  4. Noriyuki Kawashima
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  5. Kazumasa Nomoto
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  6. Masaru Wada
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  7. Jiro Kasahara
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Correspondence to Makoto Noda.

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Noda, M., Yoneya, N., Hirai, N. et al. Two causes of source/drain series resistance in bottom-contact pentacene thin-film transistors. MRS Online Proceedings Library 814, 225–230 (2004). https://doi.org/10.1557/PROC-814-I4.4

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