This paper reports on hydrogenated amorphous silicon (a-Si:H) vertical thin film transistors (VTFTs) with channel length of 100 nm, using conventional planar TFT processing technology. The device has a fully self-aligned vertical channel structure, which is highly insensitive to the non-uniformity of reactive ion etching (RIE). Therefore, the VTFT process is very suitable for large-area electronics. Presently, we can demonstrate VTFTs with remarkable ON/OFF current ratio of more than 108, low leakage current down to 1 fA, and good subthreshold slope of 0.8 V/dec at Vd = 1.5 V. The impacts of contemporary device issues, such as short-channel effects and contact resistance, on the performance of short-channel VTFTs and suggested avenues for improvement are discussed.
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This work is supported by the DALSA/NSERC Industrial Research Chair Program, Communications and Information Technology Ontario (CITO), and the Natural Sciences and Engineering Research Council of Canada (NSERC). The authors would like to thank Dr. Denis Striakhilev from α-SiDIC research group for technical assistance.
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Chan, I., Nathan, A. 100-nm Channel Length a-Si:H Vertical Thin Film Transistors. MRS Online Proceedings Library 814, 12–17 (2004). https://doi.org/10.1557/PROC-814-I2.4/A3.4