We have demonstrated a uniform, robust interface for high-k deposition with significant improvements in device electrical performance compared to conventional surface preparation techniques. The interface was a thin thermal oxide that was grown and then etched back in a controlled manner to the desired thickness. Utilizing this approach, an equivalent oxide thickness (EOT) as low as 0.87 nm has been demonstrated on high-k gate stacks having improved electrical characteristics as compared to more conventionally prepared starting surfaces.
This is a preview of subscription content, access via your institution.
Buy single article
Instant access to the full article PDF.
Tax calculation will be finalised during checkout.
H.R. Huff, A. Hou, C. Lim, Y. Kim, J. Barnett, G. Bersuker, G.A. Brown, C.D. Young, P.M. Zeitzoff, J. Gutt, P. Lysaght, M.I. Gardner and R.W. Murto, Microelectronic Engineering, 69, No. 2–4 (September 2003), pp. 152–167.
H. Iwai, S. Ohmi, IEDM Conf. Proc., p.625, 2002.
M. I. Gardner, S. Gopalan, J. Gutt, J. Peterson, H-J Li, and H.R. Huff, International Workshop of Gate Insulators, November 2003, Tokyo, Japan, p. 170
Naim Moumen, Joel Barnett, Robert W. Murto, Mark Gardner, Byoung Hun Lee, Gennadi Bersuker and Howard R. Huff, Physics and Technology of High-K Gate Dielectrics - II, Eds. S. Electrochemical Society Proceedings Series, Pennington, NJ (2003), p. 59.
J.R. Hauser, K. Ahmed, AIP Conf. Proc., 449, No. 1 (1998), p. 235.
B. Foran, J. Barnett, P.S. Lysaght, M.P. Agustin, S. Stemmer, “Characterization of advanced gate stacks for Si CMOS by electron energy loss spectroscopy in scanning transmission electron microscopy” accepted for publication to the J. of Electron Spectroscopy, March, 2004.
S. Stemmer, Z. Q. Chen, C. G. Levi, P. S. Lysaght, B. Foran, J. A. Gisby, and J. R. Taylor, Jap. J. Appl. Phys. Part 1 42, 3593 (2003).
The authors thank the people in the International SEMATECH Advanced Tool Development Facility with the help in processing of wafers.
About this article
Cite this article
Barnett, J., Moumen, N., Gutt, J. et al. Experimental Study of Etched Back Thermal Oxide for Optimization of the Si/High-k Interface. MRS Online Proceedings Library 811, 61–66 (2003). https://doi.org/10.1557/PROC-811-E1.4