Experimental Study of Etched Back Thermal Oxide for Optimization of the Si/High-k Interface


We have demonstrated a uniform, robust interface for high-k deposition with significant improvements in device electrical performance compared to conventional surface preparation techniques. The interface was a thin thermal oxide that was grown and then etched back in a controlled manner to the desired thickness. Utilizing this approach, an equivalent oxide thickness (EOT) as low as 0.87 nm has been demonstrated on high-k gate stacks having improved electrical characteristics as compared to more conventionally prepared starting surfaces.

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The authors thank the people in the International SEMATECH Advanced Tool Development Facility with the help in processing of wafers.

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Correspondence to Joel Barnett.

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Barnett, J., Moumen, N., Gutt, J. et al. Experimental Study of Etched Back Thermal Oxide for Optimization of the Si/High-k Interface. MRS Online Proceedings Library 811, 61–66 (2003). https://doi.org/10.1557/PROC-811-E1.4

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