Ultra-Shallow Junction Formation Technology from the 130 to the 45 nm node


One of the main materials challenges of the 130 nm silicon technology node was the need to find a processing solution to the anomalous diffusion behavior of ion-implanted dopants known from three decades of research. Reduction of implantation energy no longer proved sufficient when trying to reduce source/drain extension junction depth, increase abruptness, and limit sheet resistance. Spike-annealing, a new process in which ion implanted silicon could be heated rapidly to temperatures required for dopant activation and then cooled down without dwelling at temperature, adequately addressed the scaling requirements of this node. The resulting junctions achieved high dopant concentration values very close to the surface while limiting junction depth. However, this increased the propensity for dopant migration to overlying layers associated with the source/drain spacer. Loss of device performance due to this and other phenomena became a strong motivating factor for further materials research in order to sustain progress through the 130 nm and 90 nm nodes. Complex interactions between various layers have been understood and the resulting developments in spacer materials have enabled high performance devices. The requirements of the 65 and 45 nm nodes stretch spike-annealing to its limit and newer Ultra-High Temperature anneals must be considered.

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  1. 1.

    G. Dearnaley, J. H. Freeman, R. S. Nelson and J. Stephen, Ion Implantation; American Elsevier Publishing Co.: New York, (1973).

    Google Scholar 

  2. 2.

    R. F. Webber, R. S. Thornton and L. N. Large, Int. J. Electronics 26, 163 (1969).

    CAS  Article  Google Scholar 

  3. 3.

    J. C. North and W. M. Gibson, Appl. Phys. Lett., 16, 126 (1970).

    CAS  Article  Google Scholar 

  4. 4.

    Wei-Kuo Wu and Jack Washburn, J Appl. Phys. 48, 3742 (1977).

    CAS  Article  Google Scholar 

  5. 5.

    I. G. Salisbury and M. H. Loretto, Phil. Mag., 39, 317 (1979).

    CAS  Article  Google Scholar 

  6. 6.

    A. E. Michel, W. Rausch and P. A. Ronsheim, Appl. Phys. Lett. 51, 487 (1987).

    CAS  Article  Google Scholar 

  7. 7.

    Martin Giles, J. Electrochem. Soc. 138, 1160 (1991).

    CAS  Article  Google Scholar 

  8. 8.

    S. C. Jain, W. Schoenmaker, R. Lindsay, P. A. Stolk, S. Decoutere, M. Willander, and H. E. Maes, J Appl. Phys. 91, 8919 (2002).

    CAS  Article  Google Scholar 

  9. 9.

    A.J. Mayur, A. Jaggi, and A. Jain, 8th International Conference on Advanced Thermal Processing of Semiconductors–RTP 2000 edited by B. Lojek, 196 (2000).

  10. 10.

    M. Mehrotra, J. C. Hu, A. Jain, S. Hattangady, V. Reddy, S. Aur and M. Rodder, Proc. Intl. Electron Devices Meeting, 419 (1999).

  11. 11.

    Amitabh Jain in Rapid Thermal and other Short-Time Processing Technologies, edited by I F. Roozeboom, J.C. Gelpey, M.C. Ozturk, K. Reid and D.L. Kwong, 197th Electrochemical Society Meeting, 33 (2000).

  12. 12.

    P. Kohli, Amitabh Jain, H. Bu, S. Chakravarthi, C. Machala, S. T. Dunham and S. K. Banerjee, J. Vac. Sci. Technol. B22, 471 (2004).

    Article  Google Scholar 

  13. 13.

    Puneet Kohli, Ph.D Dissertation, University of Texas, Austin (2003).

  14. 14.

    W. A. Lanford and M. J. Rand, J. Appl. Phys. 49, 2473 (1978).

    CAS  Article  Google Scholar 

  15. 15.

    S. Chakravarthi, P. Kohli, P. R. Chidambaram, H. Bu, A. Jain and B. Hornung, C. F. Machala in International Conference on Simulation of Semiconductor Processes and Devices–SISPAD 2003, 159 (2003).

  16. 16.

    P. M. Rousseau, P. B. Griffin, and J. D. Plummer, Appl. Phys. Lett. 65, 578 (1994).

    CAS  Article  Google Scholar 

  17. 17.

    Srinivasan Chakravarthi, P.R. Chidambaram, Charles Machala, Amitabh Jain, and Xin Zhang in Silicon Front-End Junction Formation Technologies, edited by D.F. Downey, M.E. Law, A.P. Claverie and M.J. Rendon, (Mater. Res. Soc. Proc. 717, Pittsburgh, PA, 2002).

  18. 18.

    Kaiping Liu, Jeff Wu, Jihong Chen and Amitabh Jain, IEEE ED Lett. 24, 180 (2003).

    CAS  Article  Google Scholar 

  19. 19.

    Amitabh Jain, Kaiping Liu and Zhiqiang Wu, US Patent 6713360 (2004).

  20. 20.

    M. Diebel, S. Chakravarthi, S.T. Dunham, C.F. Machala, S. Ekbote, and A. Jain in CMOS Front-End Materials and Process Technology, edited by Tsu-Jae King, Bin Yu Robert, J.P. Lander and Shuichi Saito, (Mater. Res. Soc. Proc. 765, Pittsburgh, PA, 2003).

  21. 21.

    S. McCoy, J. Gelpey, K. Elliott, J. Ross, A. Jain, L. Robertson, K.A. Gable, 7th International Workshop on the Fabrication, Characterization and Modeling of Ultra Shallow Doping Profiles in Semiconductors (2003).

    Google Scholar 

  22. 22.

    J. Goli and A. Jain, 8th International Conference on Advanced Thermal Processing of Semiconductors - RTP 2000 edited by B. Lojek, 212 (2000).

  23. 23

    Jeff C. Gelpey, Kiefer Elliott, David Camm, Steve McCoy, Jonathan Ross, D. F. Downy and E. A. Arevalo in Rapid Thermal and other Short-Time Processing Technologies III, edited by P. Timans, E. Gusev, F. Roozeboom, M. Ozturk, and D. L. Kwong, 201st Electrochemical Society Meeting, 313 (2002).

  24. 24

    J. Narayan, R.B. James, O.W. Holland and M.J. Aziz, J. of Vac. Sci. and Tech. A 3, 1836 (1985).

    Article  Google Scholar 

  25. 25.

    H. Baumgart, F. Phillipp, G.A. Rozgonyi and U. Gosele, Appl. Phys. Lett. 38, 95 (1981).

    CAS  Article  Google Scholar 

  26. 26.

    Kevin Gable, Lance Robertson, Amitabh Jain and K. S. Jones, to be published.

  27. 27.

    S. Thirupapuliyur, A. Al-Bayati, A. Mayur and Amitabh Jain, to be presented at the 205th Meeting of The Electrochemical Society, Advanced Short-Time Thermal Processing for Si- Based CMOS Devices II (2004).

    Google Scholar 

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Jain, A. Ultra-Shallow Junction Formation Technology from the 130 to the 45 nm node. MRS Online Proceedings Library 810, 275–286 (2003). https://doi.org/10.1557/PROC-810-C5.6

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