Channel engineering and junction overlap issues for ultra-shallow junctions formed by SPER in the 45 nm CMOS technology node

Abstract

The feasibility of the SPER junction process as a reasonable alternative to the spike anneal junction is proved in this work. Good control of the SCE and performance competitive results as compared to the spike junction are obtained. An analysis of the interaction between the halo dopant and the SPER junctions has been carried out; it is shown that the performance degrades with increasing halo dose as a consequence of an overlap resistance problem.

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References

  1. [1]

    R. Lindsay et al, J. Vac. Sci. Technol. B 22, 306 (2004).

    CAS  Article  Google Scholar 

  2. [2]

    B. J. Pawlak et al, J. Vac. Sci. Technol. B 22, 297 (2004)

    CAS  Article  Google Scholar 

  3. [3]

    R. Angelucci et al, J. Electrochem. Soc., vol. 134, no. 12, December 1987, p. 3130–3134

    CAS  Article  Google Scholar 

  4. [4]

    R.B. Fair, J.Electrochem. Soc., vol. 137, no. 2, August 1990, p. 667–671.

    CAS  Article  Google Scholar 

  5. [5]

    S. Severi et al, ULIS'2003 Proceedings

Download references

Acknowledgments

The authors would like to thanks Varian Semiconductor Europe for performing some of the hightilt implantations and the plijn for the device processing.

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Severi, S., Henson, K., Lindsay, R. et al. Channel engineering and junction overlap issues for ultra-shallow junctions formed by SPER in the 45 nm CMOS technology node. MRS Online Proceedings Library 810, 43–48 (2003). https://doi.org/10.1557/PROC-810-C10.5

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