Channel engineering and junction overlap issues for ultra-shallow junctions formed by SPER in the 45 nm CMOS technology node

MRS Online Proceedings Library volume 810, pages43–48(2003)Cite this article

Abstract

The feasibility of the SPER junction process as a reasonable alternative to the spike anneal junction is proved in this work. Good control of the SCE and performance competitive results as compared to the spike junction are obtained. An analysis of the interaction between the halo dopant and the SPER junctions has been carried out; it is shown that the performance degrades with increasing halo dose as a consequence of an overlap resistance problem.

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Acknowledgments

The authors would like to thanks Varian Semiconductor Europe for performing some of the hightilt implantations and the plijn for the device processing.

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Affiliations

  1. IMEC, Kapeldreef 75, 3001, Leuven, Belgium

    Simone Severi, Kirklen Henson, Richard Lindsay, Anne Lauwers & K. De Meyer

  2. K.U.Leuven, ESAT-INSYS, Kasteelpark Arenberg 10, B-3001, Heverlee, Belgium

    Simone Severi & K. De Meyer

  3. Philips Research Leuven, Belgium

    Bartek J. Pawlak & Radu Surdeanu

Authors
  1. Simone Severi
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  2. Kirklen Henson
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  3. Richard Lindsay
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  4. Anne Lauwers
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  5. Bartek J. Pawlak
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  6. Radu Surdeanu
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  7. K. De Meyer
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Severi, S., Henson, K., Lindsay, R. et al. Channel engineering and junction overlap issues for ultra-shallow junctions formed by SPER in the 45 nm CMOS technology node. MRS Online Proceedings Library 810, 43–48 (2003). https://doi.org/10.1557/PROC-810-C10.5

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