Abstract
Against a backdrop of the latest ITRS predictions for CMOS junctions, we compare methods for dopant introduction and activation, methods for making contact to these regions, and methods for measurement of material and device properties. As activation without diffusion (sub-melt laser, capacitor discharge flash, or solid phase epitaxy) becomes more feasible, the burden on Xj, Rsh and abruptness falls on the implanters, and the process margin appears slim, opening the door for other methods of doping. For contact resistance, a major component of transistor parasitics, we find that either a move to a different substrate, or from a single midgap silicide to two band-edge metals/silicides can be quite beneficial. Through the use of simple test structures, we describe a means of extracting each component of the parasitic resistance, facilitating development of materials for CMOS junctions.
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Taylor, W.J., Rendon, M.J., Verret, E. et al. Materials Challenges for CMOS Junctions. MRS Online Proceedings Library 810, 74–85 (2003). https://doi.org/10.1557/PROC-810-C1.1
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DOI: https://doi.org/10.1557/PROC-810-C1.1