Strained Silicon on Insulator wafers made by the Smart Cut™ technology


Strained Silicon On Insulator wafers are today envisioned as a natural and powerful enhancement to standard SOI and/or bulk-like strained Si layers. For MOSFETs applications, this new technology potentially combines enhanced devices scalability allowed by thin films and enhanced electron and hole mobility in strained silicon. This paper is intended to demonstrate by experimental results how a layer transfer technique such as the Smart Cut™ technology can be used to obtain good quality tensile Strained Silicon On insulator wafers. Detailed experiments and characterizations will be used to characterize these engineered substrates and show that they are compatible with the applications.

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The authors want to acknowledge the teams of LETI and SOITEC that made this work possible. This program has been supported by the French “Réseau Micro-Nanotechnologies (RMNT)” and the French “Ministère de l'Industrie”.

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Correspondence to B. Ghyselen.

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Ghyselen, B., Bogumilowicz, Y., Aulnette, C. et al. Strained Silicon on Insulator wafers made by the Smart Cut™ technology. MRS Online Proceedings Library 809, 23 (2003).

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