A Dimple-Array Interconnect Technique for Power Semiconductor Devices


This paper describes a wireless-bond interconnect technique, termed Dimple-Array Interconnect (DAI) technique for packaging power devices. Electrical connections onto the devices are established by soldering arrays of dimples pre-formed on a metal sheet. Preliminary experimental and analytical results demonstrated potential advantages of this technique such as reduced parasitic noises, improved heat dissipation, as well as lowered processing complexity, compared to the conventional wire bonding technology in power module manufacturing. Thermomechanical analysis using thermal cycling test and FEM were also performed to evaluate the reliability characteristics of this interconnect technique for power devices.

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  1. 1

    Vic Temple, ThinPak Technology Shrinks Power Modules, Power Hybrids and Ultra-High Speed Switching Devices, PCIM, pp. 32–38, May 2000.

    Google Scholar 

  2. 2

    R. Fisher, R. Fillion, J. Burgess, and W. Hennessy, High Frequency, Low Cost, Power Packaging Using Thin Film Power Overlay Technology, Proceedings of IEEE Applied Power Electronics Conference, pp. 12–17, May, 1995.

    Google Scholar 

  3. 3

    B. Ozmat, C. S. Korman, P. McConnelee, M. Kheraluwala, E. Delgado and R. Fillion, New Power Module Packaging for Enhanced Thermal Management, Las Vegas, Nevada, May 2000.

    Google Scholar 

  4. 4

    Jon Klein, Bottomless SO-8 Package Boosts MOSFET Performance, PCIM, pp. 110, May 2000.

    Google Scholar 

  5. 5

    S. Haque, K Xing, G-Q. Lu, D. J. Nelson, D. Borojevic and F.C. Lee, “Packaging for Thermal Management of Power Electronics Building Blocks Using Metal Posts Interconnected Parallel Plate Structure”, in Proceedings of the Sixth Intersociety Conference on Thermal and Thermal-mechanical Phenomena in Electronic Systems, 1998.

    Google Scholar 

  6. 6

    Zhenxian Liang, Multilayer Integration Technology for Packaging of IPEM, Proceedings of 17th Annual VPEC Seminar, Blacksburg, VA, USA, September 19-21, 1999

    Google Scholar 

  7. 7

    Xingsheng Liu, Xiukuan Jing, and Guo-Quan Lu, Chip-scale Packaging of Power Devices and its Application in Integrated Power Electronics Module, Proceedings of IEEE ECTC Conference, pp. 290–296, Las Vegas, NV, May 2000.

    Google Scholar 

  8. 8

    Simon Wen and Guo-Quan Lu, Finite-element Modeling of Thermal and Thermomechanical Behavior for Three-dimensional Packaging of Power Electronics Modules, Proceeding of the 7th Intersociety Conference on Theraml and Thermomechanical Phenomena in Electronic Systems, Vol. II, pp. 303–309, Las Vegas, Nevada, May 23-26, 2000.

    Google Scholar 

  9. 9

    Bor Zen Hong, Thermal Fatigue Analysis of a CBGA Package with Leadfree Solder Fillets, InterSociety Conference on Thermal Phenomena, pp. 220–228, Seattle, WA, USA, May 6, 1998.

    Google Scholar 

  10. 10

    L. S. Goldmann, Geometric Optimization of Controlled Collapse Interconnections, IBM J. Research & Development, v. 13, no. 3, May 1969, pp. 251–265.

    Article  Google Scholar 

  11. 11

    R. Satoh, K. Arakawa, M. Harada, and K. Matsui, Thermal Fatigue Life of Pb-Sn Alloy Interconnections, IEEE Trans. On CHMT, 14(1), pp.224–232, March 1991.

    CAS  Google Scholar 

  12. 12

    Bor Zen Hong, and Sudipta K. Ray, Ceramic Column Grid Array Technology with Coated Solder Columns, 2000 Electronic Components and Technology Conference, May 2000, pp. 1347–1353.

    Google Scholar 

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Correspondence to Simon S. Wen.

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Wen, S.S., Huff, D. & Lu, GQ. A Dimple-Array Interconnect Technique for Power Semiconductor Devices. MRS Online Proceedings Library 682, 53 (2001). https://doi.org/10.1557/PROC-682-N5.3

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