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Advanced Ion Implantation Technology for High Performance Transistors

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Abstract

Cryo-implantation technology is proposed for reducing crystal defects in Si substrates. The substrate temperature was controlled to be below at -160°C during ion implantation. No dislocation was observed in the implanted layer after rapid thermal annealing. Pn junction leakage was successfully reduced by one order of magnitude as compared with room temperature implantation. Precise dose control is indispensable in channel region of high performance MOSFETs. In order to improve the precision of implanted dose, chip size implantation technology without photoresist mask was developed. In this technology, chip-by-chip implantation can be carried out by step-and-repeat wafer stage, and different implantation conditions are available in the same wafer independent of wafer size.

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Authors and Affiliations

  1. TOSHIBA CORPORATION, Process & Manufacturing Eng. Center, Semiconductor Company, TOSHIBA Corporation, 8, Shinsugita-cho, Isogo-ku, 235-8522, Yokohama, Japan

    Kyoichi Suguro, Atsushi Murakoshi, Toshihiko Iinuma, Haruko Akutsu, Takeshi Shibata, Yoshikazu Sugihara & Katsuya Okumura

  2. Tokyo University, 4-6-1 Komaba, Meguro-ku, 153-8904, Tokyo, Japan

    Katsuya Okumura

Authors
  1. Kyoichi Suguro
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  2. Atsushi Murakoshi
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  3. Toshihiko Iinuma
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  4. Haruko Akutsu
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  5. Takeshi Shibata
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  6. Yoshikazu Sugihara
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  7. Katsuya Okumura
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Corresponding author

Correspondence to Katsuya Okumura.

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Suguro, K., Murakoshi, A., Iinuma, T. et al. Advanced Ion Implantation Technology for High Performance Transistors. MRS Online Proceedings Library 669, 13 (2001). https://doi.org/10.1557/PROC-669-J1.3

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  • DOI: https://doi.org/10.1557/PROC-669-J1.3

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