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Improved Performance and Reliability in Aggressively-Scaled Nmos and Pmos Fets: I) Monolayer Interface Nitridation and II) Replacement of Stacked Oxide/Nitride Dielectrics with Optimized Oxide/Oxynitride Stacks

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Abstract

This paper demonstrates optimized performance and reliability in ‘second generation’ gate dielectrics which include monolayer nitrided Si-SiO2 interfaces, and deposited silicon oxynitride alloy gate dielectrics. Devices with oxynitride alloy gate dielectrics with an approximate 2:1 ratio of N:O display reduced tunneling current, improved hole mobilities and improved reliability compared to devices with Si-nitride gate dielectrics and the same nitrided interface.

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Acknowledgments

SRC, SEMATECH, the NSF and the ONR are acknowledged for research support.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering Physics, North Carolina State University, Raleigh, NC, 27695-8202, USA

    Hanyang Yang & Gerry Lucovsky

  2. Department of Materials Science and Engineering, North Carolina State University, Raleigh, NC, 27695-8202, USA

    Hiro Niimi & Gerry Lucovsky

  3. Department of Physics, North Carolina State University, Raleigh, NC, 27695-8202, USA

    Gerry Lucovsky

Authors
  1. Hanyang Yang
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  2. Hiro Niimi
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  3. Gerry Lucovsky
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Yang, H., Niimi, H. & Lucovsky, G. Improved Performance and Reliability in Aggressively-Scaled Nmos and Pmos Fets: I) Monolayer Interface Nitridation and II) Replacement of Stacked Oxide/Nitride Dielectrics with Optimized Oxide/Oxynitride Stacks. MRS Online Proceedings Library 592, 185–190 (1999). https://doi.org/10.1557/PROC-592-177

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  • DOI: https://doi.org/10.1557/PROC-592-177

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