In a Mixed-Signal IC, both digital and analog circuits exist on the same chip. Analog circuit blocks require technology attributes like precise device matching, low parametric drifts and low noise. These requirements raise additional reliability issues, over and above the reliability concerns associated with digital circuits. CMOS device reliability for mixed-signal technologies can be enhanced by modifying device architecture and improving gate oxide integrity. Interconnect metallurgy plays an important role in determining electromigration related contact/via resistance change which may impact matching of devices and resistor pairs. Appropriate source/drain engineering, device design and utilizing nitrided gate oxide has been shown to produce extremely stable devices. This article will cover process architecture and material issues related with device stability and interconnect metallurgy issues related with contact/via stability, especially with W-Plugs.
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J. H. Huang, Z. H. Liu, M. C. Jeng, P. K. Ko, and C. Hu, “A physical model for MOSFET output resistance,” IEDM, p. 569, 1992.
L. T. Su, J. A. Yasaitis, and D. A. Antoniadis, “A high-performance scalable submicron MOSFET for mixed analog/digital applications”, IEDM, p. 367, 1991.
H. S. Chen, J. Zhao, C. S. Teng, L. Moberly, and R. Lahri, “Submicron Large-Angle-Tilt Implanted Drain Technology for Mixed-Signal Applications,” IEDM, p. 91, 1994.
T. Hori and K. Kurimoto, “Deep-submicrometer large-angle-tilt implanted drain (LATID) technology,” IEEE Trans. Electron Devices, p. 2312, 1992.
C. G. Sodini, S. S. Wong, and P. K. Ko, “A framework to evaluate technology and device design enhancements for MOS integrated circuits,” IEEE J. of solid-state circuits, p. 118, 1989.
J. E. Chung, K. N. Quader, C. G. Sodini, P. K. Ko, and C. Hu, “The effect of hot-electron degradation on analog MOSFET performance,” IEDM, p. 553, 1990.
R. Rakkhit et al, “Process induced oxide damage and its implications to device reliability of submicron transistors,” 31st Ann. Pro., IRPS, p. 293, 1993.
S. Fang et al, “A new model for thin oxide degradation from wafer charging in plasma etching,” IEDM tech. Dig., p. 61, 1992.
C. Hu, J. Zhao, G. P. Li, P. Liu, E. Worley, J. White, and R, Kjar, “The effects of plasma etching induced gate oxide degradation on MOSFET’s 1/f noise,” IEEE Electron Device Lett. vol. 16, No. 2, pp. 61–63.
J. R. Black, IEEE Trans. Electron Devices ED-16 (1969) p. 338.
K. Gadepally, S. Geha, E. Myers, and Michael E. Thomas, “Electromigration Properties and their Correlation to the Physical Characteristics of Multilevel Metallizations”, Pg 301, Vol. 338 MRS Proceedings, 1994.
Kamesh Gadepally, Padala Krishna Reddy, Siew Hiew, Richard Merrill, Rajeeva Lahri, and Madan Biswal, “Effect Of, TiW As Adhesion Layer, And, Underlying Metal On Electromigration Characteristics of Tungsten Via Plugs”, MRS Proceedings, 1993.
A. Enver, and J. J. Clement, “Finite Element Numerical Modeling of Currents in VLSI Interconnects”, VMIC Conference Proceedings, Pg 149, 1990.
Anant G. Sabnis, “VLSI Reliability - VLSI Electronics Microstructure Science” Vol 22. pg 66, Academic Press, 1990.
T. Turner and K. Wendel, Proceedings of the 23rd IEEE IRPS, 1985, pp 142–147.
S. A. Lytle and A.S. Oates, “The effect of stress-induced voiding on electromigration”, J. Appl.Phys. 71 (1), 1 January 1992 pp. 174–178.
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Lahri, R., Chen, HS., Zhao, J. et al. Reliability Issues with Mixed-Signal CMOS Technology. MRS Online Proceedings Library 391, 47 (1995). https://doi.org/10.1557/PROC-391-47