Abstract
A new type of silicon-based Vertical MOSFET concept is presented, Single-Device CMOS (SD-CMOS), in which the same structure can be operated as NFET or as PFET, depending on the biasing conditions [1,2]. SD-CMOS offers new possibilities for simpler CMOS integration schemes; one of them requiring only 4 masks for the “Front-End”; with less cost to manufacture than any integration scheme requiring the fabrication of two devices with opposite doping polarities. Numerical simulations with a commercial device simulator [3] confirm the validity of the concept and demonstrate its feasibility for scaling to 10nm channel lengths.
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References
- 1
Carlos J. R. P. Augusto, US Patent No. 6 674 099, (6 January 2004).
- 2
Carlos J. R. P. Augusto, US Patent No. 7 023 030 (4 April 2006).
- 3
DESSIS 2D device simulator, ISE Integrated Systems Engineering AG, TCAD release 10.0.
- 4
M.V. Fischetti, S. Jin, T.-W. Tang, P. Asbeck, Y. Taur, S. E. Laux, N. Sano, IEEE 13th International Workshop on Computational Electronics, 2009, IWCE ‘09; DOI: 10.1109/IWCE.2009.5091145.
- 5
J. C. Sturm, H. Manoharan, L. C. Lenchyshyn, M. L. W. Thewalt, N. L. Rowell, J.-P. Noël, D. C. Houghton, Phys. Rev. Lett. 66, pp. 1362–1365, (1991); DOI: 10.1103/PhysRevLett.66.1362.
- 6
K. Eberl, K. Brunner and W. Winter, Thin Solid Films, 294 (1–2), pp. 98–104 (1997); DOI: 10.1016/S0040-6090(96)09269-3.
- 7
P. M. Solomon and S. E. Laux, IEDM Tech. Dig., 2001, pp. 95–98; DOI: 10.1109/IEDM.2001.979425.
- 8
I. O’Connor, J. Liu, F. Gaffiot, F. Prégaldiny, C. Lallement, C. Maneux, J. Goguet, S. Frégonèse, T. Zimmer, L. Anghel, T.-T. Dang, R. Leveugle, “CNTFET Modeling and Reconfigurable Logic-Circuit Design”, IEEE Trans. Circ. Syst.—I, Vol. 54, No. 11, Nov. 2007, pp. 2365–2379; DOI: 10.1109/TCSI.2007.907835.
- 9
W. J. Yu, U. J. Kim, B. R. Kang, I. H. Lee, E.-H. Lee, Y. H. Lee, “Adaptive Logic Circuits with Doping-Free Ambipolar Carbon Nanotube Transistors”, NANO LETTERS, 2009 Vol. 9, No. 4, 1401–1405; DOI: 10.1021/nl803066v.
- 10
K. Jabeur, D. Navarro, I. O’Connor, P. E. Gaillardon, M. H. B. Jamaa, F. Clermidy, “Reducing transistor count in clocked standard cells with ambipolar double-gate FETs”, Nanoscale Architectures (NANOARCH), 2010 IEEE/ACM International Symposium on, 17–18 June 2010, pp. 47–52; DOI:10.1109/NANOARCH.2010.5510928.
- 11
See for example Proceedings of the IEEE, Vol. 98, No. 2, February 2010, “Special Issue on Circuit Technology for ULP”, with an introduction by R. H. Reuss, M. Fritze; DOI:10.1109/JPROC.2009.2037210.
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Augusto, C.J.R.P., Forester, L. A New SiGeC Vertical MOSFET: Single-device CMOS (SD-CMOS). MRS Online Proceedings Library 1252, 210 (2010). https://doi.org/10.1557/PROC-1252-I02-10
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