Microelectromechanical Systems (MEMS) market is a rapidly growing market with a wide range of devices. Most of these devices require an interaction with an electronic circuit, and with the increasing number of high performance MEMS devices that are being introduced, a demand for integrating CMOS and MEMS using high-density and low-parasitic interconnects have also been on the rise.
Unfortunately, conventional methods of integrating CMOS with MEMS cannot provide the high density and low-parasitic interconnections required by modern high performance MEMS devices, and at the same time provide the flexibility required to accommodate new devices that are made using new materials and highly innovative fabrication processes.
Heterogeneous 3D integration of MEMS and CMOS has the potential to provide both the performance and the integration flexibility; however there are two interconnect challenges that need to be addressed. This paper outlines the details of these interconnect challenges and introduces two interconnect technologies, Mechanically Flexible Interconnects (MFI) and Through-Silicon Via (TSV), developed specifically to address these challenges.
E. Mounier, L. Robin, and J. Mouly, Emerging MEMS: Technologies & Markets, 2010 Report, Lyon, France: Yole, 2010.
A. Witvrouw, F. Van Steenkiste, D. Maes, L. Haspeslagh, P. Van Gerwen, P. De Moor, S. Sedky, C. Van Hoof, A.C. de Vries, A. Verbist, A. De Caussemaeker, B. Parmentier, and K. Baert, “Why CMOS-integrated transducers? A review,” Microsystem Technologies, vol. 6, 2000, pp. 192–199.
IC & MEMS Integration Abstract, Yole Development, 2004
H. Baltes, O. Brand, G.K. Fedder, C. Hierold, J.G. Korvink, and O. Tabata, CMOS-MEMS: Advanced Micro and Nanosystems, Wiley-VCH, 2005.
M. Lishchynska, C. O’Mahony, O. Slattery, O. Wittler, and H. Walter, “Evaluation of Packaging Effect on MEMS Performance: Simulation and Experimental Study,” IEEE Transactions on Advanced Packaging, vol. 30, 2007, pp. 629–635.
D. Pustan, E. Rastiagaev, and J. Wilde, “In situ analysis of the stress development during fabrication processes of micro-assemblies,” Electronic Components and Technology Conference, 2009. ECTC 2009. 59th, 2009, pp. 117–124.
M. Rahim, J. Suhling, D. Copeland, M. Islam, R. Jaeger, P. Lall, and R. Johnson, “Die stress characterization in flip chip on laminate assemblies,” Components and Packaging Technologies, IEEE Transactions on, vol. 28, 2005, pp. 415–429.
E. M. Chow, D. De Bruyker, I. Shubin, J. Cunningham, B. Cheng, K. Sahasrabuddhe, Y. Luo and J. Simons, “Microspring characterization and flip chip assembly reliability,” 42nd International Symposium on Microelectronics (IMAPS), San Jose, CA, Nov. 2009.
Q. Zhu, L. Ma and S. K. Sitaraman, “β-Helix: A lithography-Based Compliant Off-Chip Interconnect,” IEEE Transactions on Components and Packaging Technologies, Vol.26, No.3 (2003), pp.582–590.
Q. Zhu, L. Ma and S. K. Sitaraman, “Design Optimization of One-Turn Helix: A Novel Compliant Off-chip Interconnect,” IEEE Transactions on Advanced Packaging, Vol.26, No.2 (2002), pp.106–112.
M. S. Bakir, H.A. Reed, H.D. Thacker, C.S. Patel, P.A. Kohl, K.P. Martin, and J.D Meindl, “Sea of Leads (SoL) Ultrahigh Density Wafer-Level Chip Input/Output Interconnections for Gigascale Integration (GSI),” IEEE Transactions on Electron Devices, vol.50, no.10 (2003) pp.2039–2048.
N. Basavanhally et al, “High-Density Solder Bump Interconnect for MEMS Hybrid Integration,” Advanced Packaging, IEEE Transactions on, Vol. 30, 2007, pp. 622–628.
J. Mitchell et al., “Integrating Novel Packaging Technologies for Large Scale Computer Systems,” Proc. Of InterPACK, July 2009.
I. Shubin et al. “Novel packaging with rematable spring interconnect chips for MCM,” 59th Electronic Components and Technology Conference, San Diego, CA, USA: 2009, pp. 1053–1058.
H. S. Yang, R. Ravindran, M.S. Bakir and J.D. Meindl, “A 3D Interconnect System for Large Biosensor Array and CMOS Signal-Processing IC Integration,” Proc. of IEEE International Interconnect Technology Conference, Burlingame, CA, June 2010.
R. Ravindran, J. A. Sadie, K. E. Scarberry, H. S. Yang, M. S. Bakir, J. F. McDonald, and J. D. Meindl, “Biochemical Sensing with an Arrayed Silicon Nanowire Platform,” Proc. IEEE 60th Electronic Components and Technology Conference, June 2010
L. Leung and K. Chen, “Microwave characterization and modeling of high aspect ratio through-wafer interconnect vias in silicon substrates,” IEEE Transactions on Microwave Theory and Techniques, vol. 53, 2005, pp. 2472–2480.
J. Lai, H. S. Yang , H. Chen , C. King , J. Zaveri , R. Ravindran and M. S. Bakir, “A ‘mesh’ seed layer for improved through-silicon-via fabrication,” Journal of Micromechanics and Microengineering, Vol. 20, No. 2 (2010).
About this article
Cite this article
Yang, H.S., Bakir, M.S. Interconnect Technologies for Heterogeneous 3D Integration: CMOS and MEMS. MRS Online Proceedings Library 1249, 901 (2010). https://doi.org/10.1557/PROC-1249-F09-01