CMOS-Compatible Through Silicon Vias for 3D Process Integration


As the limits of traditional CMOS scaling are approached, process integration has become increasingly difficult and resulting in a diminished rate of performance improvement over time. Consequently, the search for new two- and three- dimensional sub-system solutions has been pursued. One such solution is a silicon carrier-based System-on-Package (SOP) that enables high-density interconnection of heterogeneous die beyond current first level packaging densities. Silicon carrier packaging contains through silicon vias (TSV), fine pitch Cu wiring and high-density solder pads/joins, all of which are compatible with traditional semiconductor methods and tools. These same technology elements, especially the through silicon via process, also enable three dimensional stacking and integration. An approach to fabricating electrical through-vias in silicon is described, featuring annular-shaped vias instead of the more conventional cylindrical via. This difference enables large-area, uniform arrays to be produced with high yield as it is simpler to integrate into a conventional CMOS back-end-of-line (BEOL) process flow. Furthermore, the CTE-matched silicon core provides improved mechanical stability and the dimensions of the annular via allows for metallization by various means including copper electroplating or CVD tungsten deposition. An annular metal conductor process flow will be described. Through-via resistance measurements of 50, 90, and 150μm deep tungsten-filled annular vias will be compared. Two silicon carrier test vehicle designs, containing more than 2,200 and 9,600 electrical through-vias, respectively, were built to determine process yield and uniformity of via resistance. Through silicon via resistances range from 15-40 mΩ, and yields in excess of 99.99% have been demonstrated.

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  1. 1.

    Tsang, C.K. and A.W. Topol, “3D Integrated Circuits and Silicon Carrier Packaging Realization,” Proceedings of the 23rd VLSI VMIC Conference, Fremont, CA, 2006, pp. 61–69.

  2. 2.

  3. 3.

    Takahashi, K. et al., “Process Integration of 3D Chip Stack with Vertical Interconnection,” Proceedings of the 54th Electronic Components and Technology Conference, Las Vegas, NV, 2004, pp. 601–609.

  4. 4.

    Ramm, P. et al., “3D System integration Technologies,” Materials Research Society Symposium Proceedings, San Francisco, CA, 2003, pp. 3–14.

  5. 5.

    Klumpp, A. et al., “Chip-to-Wafer Stacking Technology for 3D System Integration,” Proceedings of the 53rd Electronic Components and Technology Conference, New Orleans, LA, 2003, pp. 1080–1083.

  6. 6.

    Khan, N. et al., “Development of 3D Stacked Package Using Silicon Interposer for High Power Application,” Proceedings of the 56th Electronic Components and Technology Conference, San Diego, CA, 2006, pp. 756–760.

  7. 7.

    Kunio, T. et al., “Three-dimensional Shared Memory Fabricated Using Wafer Stacking Technology,” IEDM Technical Digest, 2000, pp. 165–168.

  8. 8.

    Topol, A.W. et al., “Three-dimensional Integrated Circuits,” IBM J. Res. & Dev., 50 (4/5), 2006, pp. 491–506.

    Article  Google Scholar 

  9. 9.

    Bower, C.A. et al., “High Density Vertical Interconnects for 3D Integration of Silicon Integrated Circuits,” Proceedings of the 56th Electronic Components and Technology Conference, San Diego, CA, 2006, pp. 399–403.

  10. 10.

    Patel, C.S. et al., “Silicon Carrier with Deep Through Vias, Fine Pitch Wiring and Through Cavity for Parallel Optical Transceiver,” Proceedings of the 55th Electronic Components and Technology Conf, Lake Buena Vista, FL, 2005, pp. 1318 – 1324.

  11. 11.

    Andry, P.S. et al., “A CMOS-compatible Process for Fabricating Electrical Through-vias in Silicon,” Proceedings of the 56th Electronic Components and Technology Conference, San Diego, CA, 2006, pp. 831–837.

  12. 12.

    Morimoto, R. et al., “Low-Resistivity Phosphorus-Doped Polycrystalline Silicon Thin Films Formed by Catalytic Chemical Vapor Deposition and Successive Rapid Thermal Annealing,” Jpn. J. Appl. Phys., 41 (2A), 2002, pp. 501–506.

    CAS  Article  Google Scholar 

  13. 13.

    Suzuki, K. et al., “Resistivity of Heavily Doped Polycrystalline Silicon Subjected to Furnace Annealing,” Jpn. J. Appl. Phys., 34 (4A), 1995, pp. 1748–1752.

    CAS  Article  Google Scholar 

  14. 14.

    Chang, I.S. and M.H. Hon, “Growth characteristics and electrical resistivity of chemical vapor-deposited tungsten film”, Thin Solid Films, 333 (1/2), 1998, pp. 108–113.

    CAS  Article  Google Scholar 

  15. 15.

    Wright, S.L. et al., “Characterization of Micro-bump C4 Interconnects for Si-Carrier SOP Applications,” Proceedings 56th Electronic Components and Technology Conference., San Diego, CA, 2006, pp. 633–640.

  16. 16.

    Manzer, D. et al., “High-speed electrical testing of multichip ceramic modules,” IBM J. Res. Dev., 49 (4/5), 2005, pp. 687–697.

    Article  Google Scholar 

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Correspondence to Cornelia K. Tsang.

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Tsang, C.K., Andry, P.S., Sprogis, E.J. et al. CMOS-Compatible Through Silicon Vias for 3D Process Integration. MRS Online Proceedings Library 970, 101 (2006).

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