Low complexity look up table based adaptive digital predistorter with low memory requirements
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With the advent of spectrally efficient wireless communication systems employing modulation schemes with varying amplitude of the communication signal, linearization techniques for nonlinear microwave power amplifiers (PAs) have gained significant interest. In this article, a low complexity, direct-learning multilevel lookup table based adaptive digital predistortion technique has been proposed to linearize a PA. A loop delay compensation scheme has been used to achieve a significant reduction in convergence time and an improvement in linearization accuracy in the presence of an unknown loop delay. Compared with the conventional predistorters, the proposed technique shows fast adaptation speed which enables the predistorter to track time-varying PA nonlinearities.
KeywordsError Vector Magnitude Feedback Path Wideband Code Division Multiple Access High Convergence Rate Loop Delay
Power amplifiers (PAs) are important components in a communication system, but they are inherently nonlinear. The nonlinearity produces spectral re-growth, which leads to adjacent channel interference and violations of the out of band emission standards. It also causes in band distortion, which degrades the bit error rate and data throughput of the communication system. To reduce the nonlinearity, the PA can be backed off so that it operates within the linear portion of its operating region. However, newer transmission formats, such as wideband code division multiple access, have large fluctuations in their signal envelopes, i.e., high peak-to-average power ratios. This means that the PA needs to be backed off well below its maximum saturated output power in order to handle infrequent peaks, which result in very low efficiencies.
DPD works entirely in the digital domain and is already in use in 2G systems. The techniques are mostly based on look up tables (LUTs) , using a memory-less characteristic of the PA. With large signal bandwidths as in 3G systems, memory effects become more pronounced . Therefore, for such systems memory-less LUT approach will be of no use. Some of the noted work on LUT-based DPD can also be found in [6, 7, 8]. In this article, attention is focused on the development of an adaptive LUT-based DPD linearization technique which solve the linearization problem in an optimal way.
In the following sections, an adaptive DPD technique is modeled and simulated. The aim of this article is to develop a linearization technique which is less complex and requires less memory from FPGA implementation point of view.
In Section 2, the basic approach is described. In the last section, the simulation of the system and the computation of the LUT values have been reported.
2. Basic approach used in design of adaptive digital predistorter
LUT-based digital predistorters have low computational complexity, but they require significantly more memory space to store the model parameters than polynomial-based digital predistorters. Thus, LUT-based digital predistorters have slow convergence speed as compared to polynomial-based digital predistorters. Comparatively, evaluation of a polynomial function is more computationally complex than a simple memory LUT entry and compensation of higher orders of nonlinearity and memory effects requires a high order polynomial. For newer spectral efficiency transmission formats, a predistorter bandwidth of several tens of MHz might be required for implementation of these high order polynomials. In this article, a novel low complexity LUT-based adaptive digital predistorter with reduced memory requirements has been proposed by using interpolation and efficient spacing of table entries, which leads to low LUT requirement. The proposed adaptive digital predistorter has much higher convergence rate as compared to other LUT-based adaptive digital predistorters.
Functions f ρ (x) and f θ (x) denote the nonlinear AM-AM and AM-PM distortions of PA. The polar predistorter consists of two LUTs that approximate the inverse function of the PA's amplitude distortion and the phase compensation function h θ (x) = -f θ (x).
For computing the error in determining h ρ (x) and h θ (x), consider the n th entry of the amplitude LUT. For input amplitude, x i = x n +ε x with 0 < ε x ≤ d n , where d n = xn+1-x n is the width of the n th interval, the output of the LUT predistorter will be h ρ (x i )+ε hρ . Because the calculation in error of h ρ (x) and h θ (x) is similar. So, only derivation for calculating the error ε hρ in determining h ρ (x) will be presented, and is as follows:
where p(x) is the probability density function (PDF) of the input amplitude and is the PDF of the predistorted amplitude of the input signal. Equations (22) and (23) show that the mean-squared amplitude and phase errors are inversely proportional to N4, which is a much faster rate of decrease than , which results in a MSE that is inversely proportional to only N2.
3. Proposed design
p(r) and are the PDFs of the input amplitude and predistorted amplitude, respectively. Also by using an optimal compander, the total residual distortion power at the PA output remains inversely proportional to N4 as given in Equations (22) and (23) from simulation results it has been observed that the residual distortion power decreases by 12 dB when the LUT size is doubled as opposed to 6 dB. Thus, combination of linear interpolation with optimal spacing results in higher improvements in PA nonlinearity.
Here, one thing that must be considered is that the compander is implemented as an LUT. It is therefore critical that the additional memory requirements do not offset the gains obtained from using optimal spacing. Thus, the compander has to be implemented as a uniformly spaced, linearly interpolated LUT of size L, forming a piece-wise linear function. From simulation results, it has been observed that as compared to uniform spacing the value of error vector magnitude (EVM) improves by about 10 dB when the LUT size was kept as 256. Also it was observed that as the size of L has been increased beyond 256, no much improvement was found in EVM. Also when both uniform spaced and optimal spaced predistorters were implemented using VHDL synthesis, the gate count has shown almost two times reduction in case of optimally spaced compander.
The correlation between the input and feedback signal is performed on a modulated signal that precedes the training signal because the gain compression of the amplifier makes the accuracy of the correlation over the training signal suspect. In addition, because the envelope of the modulated signal will typically have a PDF such that it spends much of its time within the linear operating region of the amplifier, correlation using the modulated signal becomes more reliable. However, because the modulated signal is stochastic, the statistics of the modulated signal, as well as the size of the data block over which the correlation operation is performed will impact the accuracy of the delay estimation. In general, the accuracy of the estimation improves as the block size increases. Unfortunately, a larger block size requires more memory and takes longer to perform the estimate. The predistortion function cannot be exactly determined following the transmission of single training ramp and recalculation of the LUT coefficients thereafter. A series of training ramps will have to be transmitted. Although significant improvement in the ACPR of the amplifier should be observed even after a single training ramp, yet simulations have shown that the predistortion function can converge to a solution after only six training ramps.
In this study, a low complexity adaptive digital predistorter with much higher convergence rate as compared to other LUT-based adaptive digital predistorters has been presented. Six training ramps have been used to get high degree of convergence. Although the proposed design shows better performance in terms of reducing EVM and improving ACLR, yet future work will be focused on FPGA implementation of the proposed technique with less hardware requirements.
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