Voltage-Polarity Dependent Programming Behaviors of Amorphous In–Ga–Zn–O Thin-Film Transistor Memory with an Atomic-Layer-Deposited ZnO Charge Trapping Layer
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Amorphous In–Ga–Zn-O (a-IGZO) thin-film transistor (TFT) memories are attracting many interests for future system-on-panel applications; however, they usually exhibit a poor erasing efficiency. In this article, we investigate voltage-polarity-dependent programming behaviors of an a-IGZO TFT memory with an atomic-layer-deposited ZnO charge trapping layer (CTL). The pristine devices demonstrate electrically programmable characteristics not only under positive gate biases but also under negative gate biases. In particular, the latter can generate a much higher programming efficiency than the former. Upon applying a gate bias pulse of +13 V/1 μs, the device shows a threshold voltage shift (ΔVth) of 2 V; and the ΔVth is as large as −6.5 V for a gate bias pulse of −13 V/1 μs. In the case of 12 V/1 ms programming (P) and −12 V/10 μs erasing (E), a memory window as large as 7.2 V can be achieved at 103 of P/E cycles. By comparing the ZnO CTLs annealed in O2 or N2 with the as-deposited one, it is concluded that the oxygen vacancy (VO)-related defects dominate the bipolar programming characteristics of the TFT memory devices. For programming at positive gate voltage, electrons are injected from the IGZO channel into the ZnO layer and preferentially trapped at deep levels of singly ionized oxygen vacancy (VO +) and doubly ionized oxygen vacancy (VO 2+). Regarding programming at negative gate voltage, electrons are de-trapped easily from neutral oxygen vacancies because of shallow donors and tunnel back to the channel. This thus leads to highly efficient erasing by the formation of additional ionized oxygen vacancies with positive charges.
KeywordsZnO In–Ga–Zn–O Nonvolatile memory Thin-film transistor (TFT) Oxygen vacancy
Atomic layer deposition
Charge trapping layer
X-ray photoelectron spectroscopy
A thin-film transistor (TFT) based on amorphous indium–gallium–zinc–oxide (a-IGZO) has been extensively studied for the application to flexible and transparent electronic systems [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]. This is attributed to some specific properties of a-IGZO films such as good uniformity, low processing temperature, visible light transparency, and high electron mobility . Other than that, a-IGZO TFT nonvolatile memories have also been proposed, and its nonvolatile data storage capability expands the scope of the a-IGZO TFT device utilization. As a typical architecture of nonvolatile memory devices, a floating-gated a-IGZO TFT memory has been intensively investigated in recent years. Up to now, various materials have been explored as a floating gate (i.e., charge storage medium), such as dielectrics [14, 15], metal nanocrystals [16, 17], and semiconducting materials [18, 19, 20, 21]. Since a-IGZO is a natural n-type semiconductor, and hole inversion is hardly realized in an a-IGZO TFT under a negative gate bias, therefore, the a-IGZO TFT memories usually have a poor erasing efficiency. In other words, most a-IGZO TFT memories cannot be electrically erased through hole injection from the channel [14, 15, 16]. Nevertheless, Zhang et al.  fabricated a TFT memory using a-IGZO as both the charge trapping layer (CTL) and the channel layer, which exhibited electrically programmable and erasable characteristics, as well as good data retention. Meanwhile, Yun et al. also investigated the characteristics of the a-IGZO TFT memories with different compositional IGZO CTL, revealing a decreasing memory window with increasing the O2 partial pressure (PO2) during sputtering deposition of the CTL . In addition, Bak et al. reported the performance of the a-IGZO TFT memories with various conductivity ZnO CTLs and inferred that the optimized electronic nature of bandgap structure for the ZnO CTL could be one of the most important factors to realize highly functional oxide TFT memories . Although the aforementioned oxide semiconductor CTL-based a-IGZO TFT memories exhibit superior electrical programming/erasing speeds, the bipolar programming characteristics of the abovementioned devices have not been reported, and the corresponding capture processes of different charges in the CTL of oxide semiconductor are not clear yet, especially for the trapping of positive charges.
In this work, a bipolar programmable a-IGZO TFT memory was fabricated by using an atomic-layer-deposited ZnO film as a CTL. By comparing the bipolar programming characteristics of the TFT memory devices with the as-deposited, O2- or N2-annealed ZnO CTLs, the capture processes of different charges in the ZnO layer were discussed. It is revealed that oxygen vacancy-related defects dominate the bipolar programming characteristics of the a-IGZO TFT memory devices.
P-type Si (100) wafers with resistivity of 0.001–0.005 Ω cm were cleaned using the standard RCA cleaning process and used as the back gate of the device. Then, 35-nm Al2O3 and 20-nm ZnO films were deposited successively by atomic layer deposition (ALD) at 250 °C and 200 °C, which served as the blocking layer and CTL of the TFT memory, respectively. It is worth mentioning that the ZnO film has a root–mean–square (RMS) roughness of 0.553 nm. Subsequently, photolithography and wet etching were performed to define the CTL of ZnO. After that, an 8-nm Al2O3 tunneling layer was grown by ALD. The precursors of diethylzinc (DEZ)/H2O and TMA/H2O were used for the growth of ZnO and Al2O3 films, respectively. Thereafter, a 40-nm a-IGZO film was deposited by radio frequency magnetron sputtering as a channel layer at room temperature by using an InGaZnO4 target. The active channel with a width (W)/length (L) of 100/10 μm was then defined by photolithography and diluted HCl etching. Source and drain contacts of Ti/Au (30 nm/70 nm) were formed by e-beam evaporation followed by a lift-off process. Finally, all the fabricated devices were annealed at 250 °C in O2 for 5 min to improve its performance. The electrical characterizations were performed by using a semiconductor parameter analyzer (Agilent B1500A) at room temperature. The threshold voltage (Vth) is defined as the gate voltage at which the drain current equals to W/L×10−9 A. The carrier concentration of ZnO films were extracted from Hall effect measurements (Ecopia HMS-3000) at room temperature.
Results and Discussion
Comparisons of the programming and erasing characteristics of various a-IGZO TFT memories with different gate stacks
In summary, we fabricated a bipolar programmable a-IGZO TFT memory with an atomic-layer-deposited ZnO CTL. Compared with the programming under a positive gate bias, the programming under a negative gate bias can generate a much higher efficiency. This is because different oxygen vacancy defects take effect during voltage-polarity-dependent programming. That is, deep defects of VO+ and VO2+ play a key role for electrons trapping during positive bias programming, and shallow defects of VO mainly donate electrons during negative bias programming, resulting in the generation of positively charged oxygen vacancies.
The authors would like to acknowledge the financial support by the National Natural Science Foundation of China (grant nos. 61874029, 61774041) and National Key Technologies Research and Development Program of China (grant no. 2015ZX02102-003).
DDL performed the experiment, data processing, and manuscript drafting. SJD and WJL modified the manuscript. Other authors help review and discuss the manuscript. All authors read and approved the final manuscript.
The authors declare that they have no competing interests.
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