Nanocrystal-Embedded-Insulator (NEI) Ferroelectric FETs for Negative Capacitance Device and Non-Volatile Memory Applications
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We report a novel nanocrystal-embedded-insulator (NEI) ferroelectric field-effect transistor (FeFET) with very thin unified-ferroelectric/dielectric (FE/DE) insulating layer, which is promising for low-voltage logic and non-volatile memory (NVM) applications. The ferroelectric nature of the NEI layers comprising orthorhombic ZrO2 nanocrystals embedded in amorphous Al2O3 is proved by polarization voltage measurements, piezoresponse force microscopy, and electrical measurements. The temperature dependent performance and endurance behavior of a NEI negative capacitance FET (NCFET) are investigated. A FeFET with 3.6 nm thick FE/DE achieves a memory window larger than 1 V, paving a pathway for ultimate scaling of FE thickness to enable three-dimensional FeFETs with very small fin pitch.
KeywordsNEI Ferroelectric NC Memory Germanium FeFET
Atomic layer deposition
Boron fluoride ion
Ferroelectric field-effect transistor
High-resolution transmission electron microscope
Metal-oxide-semiconductor field-effect transistors
Negative differential resistance
Rapid thermal annealing
In this work, NEI FeFETs are reported. Physical properties and ferroelectricity of the NEI layers with different physical thicknesses are characterized. Electrical performance of NEI FeFETs is investigated for low-voltage logic and NVM applications.
Key process steps for NEI FeFETs fabrication are shown in Fig. 1a. Four-inch n-type Ge(001) wafers with a resistivity of 0.088–0.14 Ω cm were used as the starting substrates. After pregate cleaning using diluted HF, Ge(001) wafers were loaded into an atomic layer deposition (ALD) chamber for the deposition of the NEI layer comprising ZrO2 nanocrystals embedded in amorphous Al2O3 matrix. NEI layers with the various thicknesses were utilized in this work. TaN metal gate was deposited on the NEI FeFETs using the reactive sputtering. After the gate patterning and etching, BF2+ ions were implanted into the source/drain regions at an energy of 20 keV and a dose of 1 × 15 cm−2. Thirty-nanometer nickel (Ni) was deposited in source/drain regions using the lift-off process. Finally, device fabrication was completed with rapid thermal annealing (RTA). Control metal-oxide-semiconductor field-effect transistors (MOSFETs) with a purely dielectric Al2O3 gate insulating layer also were fabricated.
Figure 1b shows the 3D schematic of the fabricated NEI FeFET, which comprises FE nanocrystals embedded in an amorphous DE gate insulating layer. Although the volume of FE material is small, it is sufficient for NCFET and NVM applications. The insulating DE material is key to achieving low gate leakage and low operating voltage; it should have both a large bandgap energy and high dielectric permittivity (κ). It also should provide for a high coercive field (Ec) of the embedded FE nanocrystals.
Results and Discussion
NEI FeFET for Non-Volatile Memory Application
Novel FeFETs with ZrO2 nanocrystals embedded in an amorphous Al2O3 gate insulating layer are reported. Physical analyses indicate that less than 0.5% Zr in Al2O3 produces sufficient ferroelectricity for NCFET and NVM applications. Stable NC effect is observed at different measurement temperatures. Stable FeFET memory operation with record thin (3.6-nm total thickness) gate insulator is demonstrated. Stable MW is achieved over 1000 DC endurance cycles. The proposed NEI FeFET design provides a pathway for scaling down the thickness of the FE/DE gate insulator layer to be compatible with FinFETs with very small fin pitches.
The authors acknowledge support from the National Natural Science Foundation of China under Grant No. 61534004, 61604112, 61622405, 61874081, and 61851406. This work was also supported by the 111 Project (B12026).
Availability of Data and Materials
The datasets supporting the conclusions of this article are included within the article.
YP carried out the experiments and drafted the manuscript. GQH, YP, and WWX designed the experiments. JBW helped to measure the device. GQH and YL helped to revise the manuscript. JCZ and YH supported the study. All the authors read and approved the final manuscript.
State Key Discipline Laboratory of Wide Band Gap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, People’s Republic of China.
The authors declare that they have no competing interests.
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
- 2.Krivokapic Z, Rana U, Galatage R, Razavieh A, Aziz A, Liu J, Shi J, Kim HJ, Sporer R, Serrao C, Busquet A, Polakowski P, Müller J, Kleemeier W, Jacob A, Brown D, Knorr A, Carter R, Banna S (2017) 14nm ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications. In: IEDM Tech. Dig, pp 357–360Google Scholar
- 3.Chung W, Si M, Ye PD (2017) Hysteresis-free negative capacitance germanium CMOS FinFETs with Bi-directional Sub-60 mV/dec. In: IEDM Tech. Dig, pp 365–368Google Scholar
- 4.Si M, Jiang C, Su C-J, Tang Y-T, Yang L, Chung W, Alam MA, Ye PD (2017) Sub-60mV/dec ferroelctric HZO MoS2 negative capacitance field-effect transistor with metal gate: the role of parasitic capacitance. In: IEDM Tech. Dig, pp 369–372Google Scholar
- 5.Su C-J, Tang Y-T, Tsou Y-C, Sung P-J, Hou F-J, Wang C-J, Chung S-T, Hsieh C-Y, Yeh Y-S, Hsueh F-K, Kao K-H, Chuang S-S, Wu C-T, You T-Y, Jian Y-L, Chou T-H, Shen Y-L, Chen B-Y, Luo G-L, Hong T-C, Huang K-P, Chen M-C, Lee Y-J, Chao T-S, Tseng T-Y, Wu W-F, Huang G-W, Shieh J-M, Yeh W-K, Wang Y-H (2017) Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved I ON. In: VLSI Tech. Symp, p TI2-1Google Scholar
- 6.Zhou J, Han G, Li Q, Peng Y, Lu X, Zhang C, Zhang J, Sun Q, Zhang DW, Hao Y (2016) Ferroelectric HfZrOx Ge and GeSn PMOSFETs with sub-60 mV/decade subthreshold swing, negligible hysteresis, and improved I DS. In: IEDM Tech. Dig, pp 310–313Google Scholar
- 7.Luc QH, Fan-Chiang CC, Huynh SH, Huang P, Do HB, Ha MTH, Jin YD, Nguyen TA, Zhang KY, Wang HC, Lin YK, Lin YC, Hu C, Iwai H, Chang EY (2018) First experimental demonstration of negative capacitance InGaAs MOSFETs with Hf0.5Zr0.5O2 ferroelectric gate stack. In: VLSI Symp, pp 47–48Google Scholar
- 8.Müller J, Yurchuk E, Schlösser T, Paul J, Hoffmann R, Müller S, Martin D, Slesazeck S, Polakowski P, Sundqvist J, Czernohorsky M, Seidel K, Kücher P, Boschke R, Trentzsch M, Gebauer K, Schröder U, Mikolajick T (2012) Ferroelectricity in HfO2 enables nonvolatile data storage in 28 nm HKMG. In: VLSI Symp, pp 25–26Google Scholar
- 9.Xiao W, Liu C, Peng Y, Zheng S, Feng Q, Zhang C, Zhang J, Hao Y, Liao M, Zhou Y (2019) Performance Improvement of Hf0.5Zr0.5O2 Based Ferroelectric-Field-Effect Transistors with ZrO2 seed layers. IEEE Electron Device Lett xx.Google Scholar
- 10.King Y-C, King T-J, Hu C (1998) MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex. In: IEDM Tech. Dig, pp 115–118Google Scholar
- 12.Peng Y, Xiao W, Han G, Wu J, Liu H, Liu Y, Xu N, King Liu T-J, Hao Y (2019) Nanocrystal-embedded-insulator ferroelectric negative capacitance FETs with sub-kT/q swing. IEEE Electron Device Lett 40:9–12Google Scholar
- 13.Ohtaka O, Yamanaka T, Kume S, Hara N, Asano H, Izumi F (2013) Phase transformation of baddeleyite (ZrO2) to an orthorhombic phase: structural analysis of ortho-ZrO2 by neutron diffraction. US Jap Sem 67:463–468Google Scholar
- 18.Narasimha S, Jagannathan B, Ogino A, Jaeger D, Greene B, Sheraw C, Zhao K, Haran B, Kwon U, Mahalingam AKM, Kannan B, Morganfeld B, Dechene J, Radens C, Tessier A, Hassan A, Narisetty H, Ahsan I, Aminpur M, An C, Aquilino M, Arya A, Augur R, Baliga N, Bhelkar R, Biery G, Blauberg A, Borjemscaia N, Bryant A, Cao L (2017) A 7nm CMOS technology platform for mobile and high performance compute application. In: IEDM Tech Dig, pp 29.5.1–29.5.4Google Scholar
- 21.Müller J, Böscke TS, Müller S, Yurchuk E, Polakowski P, Paul J, Martin D, Schenk T, Khullar K, Kersch A, Weinreich W, Riedel S, Seidel K, Kumar A, Arruda TM, Kalinin SV, Schlösser T, Boschke R, van Bentum R, Schröder U, Mikolajick T (2013) Ferroelectric hafnium oxide: A CMOS-compatible and highly scalable approach to future ferroelectric memories. In: IEDM Tech Dig, pp 280–283Google Scholar
- 22.Chiu Y-C, Cheng C-H, Chang C-Y, Lee M-H, Hsu H-H, Yen S-S (2015) Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation fast 20-ns speed and robust 85°C-extrapolated 1016 endurance. In: Symp. on VLSI Technology and Circuits, pp T184–T185Google Scholar
- 23.Chiu Y-C, Cheng C-H, Chang C-Y, Tang Y-T, Chen M-C (2016) One-transistor ferroelectric versatile memory: strained-gate engineering for realizing energy-efficient switching and fast negative-capacitance operation. In: VLSI Symp, pp 150–151Google Scholar
- 25.Müller J, Polakowski P, Riedel S, Mueller S, Yurchuk E, Mikolajick T (2013) Performance investigation and optimization of Si:HfO2 FeFETs on a 28 nm bulk technology, ISAF/PFM, pp 248–251Google Scholar
- 26.Chen K-Y, Huang Y-H, Kao R-W, Lin Y-X, Wu Y-H (2018) Dependence of reliability of ferroelectric HfZrOx on epitaxial SiGe film with various Ge content. In: VLSI Symp, pp 119–120Google Scholar
- 27.Martin D, Yurchuk E, Müller S, Müller J, Paul J, Sundquist J, Slesazeck S, Schloesser T, Bentum RV, Trentzsch M, Schroeder U, Mikojajick T (2012) Downscaling ferroelectric field effect transistors by using ferroelectric Si-doped HfO2. In: ULIS, pp 195–198Google Scholar
- 28.Zhou J, Wu J, Han G, Kanyang R, Peng Y, Li J, Wang H, Liu Y, Zhang J, Sun Q, Zhang D, Hao Y (2017) Frequency dependence of performance in Ge negative capacitance PFETs achieving sub-30 mV/decade swing and 110 mV hysteresis at MHz. In: IEDM Tech. Dig, pp 373–376Google Scholar
- 29.Lee MH, Fan S-T, Tang C-H, Chen P-G, Chou Y-C, Chen H-H, Kuo J-Y, Xie M-J, Liu S-N, Liao M-H, Jong C-A, Li K-S, Chen M-C, Liu CW (2016) Physical thickness 1.x nm ferroelectric HfZrOx negative capacitance FETs. In: IEDM Tech. Dig, pp 370–373Google Scholar
- 30.Zhou H, Kwon D, Sachid AB, Liao Y, Chatterjee K, Tan AJ, Yadav AK, Hu C, Salahuddin S (2018) Negative capacitance, n-channel, Si FinFETs: bi-directional sub-60 mV/dec, negative DIBL, negative differential resistance and improved short channel effect. In: VLSI Symp, pp 53–54Google Scholar
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