A Nanoscale Low-Power Resistorless Voltage Reference with High PSRR
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In this paper, a nano-watt resistorless subthreshold voltage reference with high-power supply rejection ratio (PSRR) is presented. A self-biased MOS voltage divider is proposed to provide bias current for whole voltage reference, which is a positive temperature coefficient (TC) current containing threshold voltage characteristics. By injecting the generated current into a transistor with a different threshold voltage, a delta threshold voltage with a greatly reduced negative TC is realized and temperature-compensated by a generated positive TC item at the same time. Therefore, a temperature-stable voltage reference is achieved in the proposed compacted method with low power consumption and high PSRR. Verification results with 65-nm CMOS technology demonstrate that the minimum supply voltage can be as low as 0.35 V with a 0.00182-mm2 active area. The generated reference voltage is 148 mV, with a TC of 28 ppm/°C for the − 30 to 80 °C temperature range. The line sensitivity is 1.8 mV/V, and the PSRR without any filtering capacitor at 100 Hz is 53 dB with a 2.28-nW power consumption.
KeywordsSubthreshold Low-power High PSRR Resistorless Nanoscale
Complementary to absolute temperature
High threshold voltage
Medium threshold voltage
Power supply rejection ratio
Proportional to absolute temperature
Voltage reference is one of the core modules in electronic systems, which is widely used in medical electronics, power managements, wireless environmental sensors, and communication circuits. As the supply voltage of electronic systems continues to decrease with technology improvement, the requirements for a low-power voltage reference with nanoscale technology are critically increasing [1, 2].
Conventional voltage references are based on a bandgap reference (BGR) circuit, which is a weighted sum of VBE and thermal voltage [3, 4]. However, due to the nonlinear temperature behavior of VBE, it is essential to use curvature compensation approaches to improve the precision of BGR [5, 6]. Another disadvantage of BGR is the power consumption. The VBE is around 0.7 V without shrinking down with process improvement, which absolutely restricts the supply voltage. These make BGRs unsuitable for low-voltage and nanoscale applications.
In order to achieve low-power operation, MOS-only subthreshold voltage references are gradually adopted [7, 8, 9, 10]. As transistors in a weak inversion region have inherent advantages in low-power applications with quite small current, the power consumption of relative voltage references can be effectively reduced. Besides, since the characteristics of metal-oxide-semiconductor field-effect transistor (MOSFET) are consistent with process improvement, voltage reference based on MOSFET is more adaptable to advanced technologies. In addition, the usage of resistors should also be avoided in low-power applications. Since the current in the voltage reference is usually inversely proportional to resistance value, low-power dissipation means high-ohmic resistors , which can induce large noise occupying a large chip area.
Power supply rejection ratio (PSRR) is another important parameter of voltage reference. Conventional solutions to improve PSRR are at the cost of chip area and power consumption, such as additional amplifiers , long channel transistors , cascode structures, and additional gain stage .
In order to overcome the mentioned issues above, a nano-watt MOSFET-based resistorless subthreshold voltage reference with high PSRR is proposed in this brief, which is suitable for advanced technology, such as nanoscale process. A self-biased MOSFET voltage divider for PSRR enhancement is adopted in the proposed voltage reference, which can generate a positive temperature coefficient (TC) current containing threshold voltage characteristics. The current serves as bias currents for the whole voltage reference. Besides, the threshold voltage embedded in the bias current is reproduced by injecting bias current into MOSFET with different threshold voltages in the paper. With the proposed method, a delta threshold voltage (∆VTH) with greatly reduced negative TC is obtained. Besides, a weighted proportional to absolute temperature (PTAT) item is also obtained, while a weighted sum of ∆VTH and PTAT voltage is realized at the same time. Due to the mutual TC cancelation of two different threshold voltages, the required PTAT voltage can be greatly reduced for temperature compensation. By this method, a MOSFET-only resistorless voltage reference is achieved by a compacted structure with low power consumption.
The start-up circuit consists of MP5, MP6, and MN4. At the beginning of a power-on stage, the gate potential of MP6 is low and MP6 is turned on. The current generated by MP6 makes the gate potential of MN1 and MN2 rise, and the whole circuit starts to work. At the same time, MP5 charges the start-up capacitor, MN4. With the charging procedure of MN4, transistor MP6 is gradually turned off, which makes the start-up circuit to be broken away from the core of the proposed voltage reference without additional power dissipation. By this method, the proposed voltage reference can work in a desired operating point while avoiding a degeneration point.
Self-Biased Current Generator
The middle part in Fig. 1 is a self-biased current generator, which is based on a MOSFET-only voltage divider. The bias current with positive TC for the whole voltage reference is generated in this part, which is relevant to the medium threshold voltage of NMOS. The unique characteristic of the presented bias current is adopted to realize the proposed voltage reference in a convenient way, which will be analyzed in the “Method” section.
where μ is the carrier mobility and COX is the oxide capacitance per unit area.
where ISQN is the specific current of NMOS and VTHN is the threshold voltage of NMOS.
As shown in Eq. (9), threshold voltage VTHN is complementary to absolute temperature (CTAT), while thermal voltage VT is proportional to absolute temperature (PTAT). As the temperature increases, VTHN/(mVT) will reduce, so that the positive current characteristics of the bias current will be enhanced.
By this method, a positive TC bias current is achieved by MOSFET-only structure, which carries the characteristics of NMOS threshold voltage.
V REF Generating Circuit
where ISQP is the specific current of PMOS and VTHP is the VTH of PMOS.
As shown in the first two items of Eq. (11), a delta threshold voltage is realized. Since VTH = VTH0 − βT, where VTH0 is the threshold voltage at 0 K and β is the TC of the threshold voltage, the generated delta threshold voltage is a complementary to the absolute temperature (CTAT) voltage with greatly shrunken TC with |βVTHP| > βVTHN. Besides, two additional PTAT voltages are simultaneously realized and shown in the last two items of Eq. (11), which are adopted to cancel the reduced TC of delta threshold voltage. Therefore, a compacted temperature-stable reference voltage is achieved without a complicated structure, which is stable at |VTHP0| − VTHN0.
Based on the previous analysis, a low-power MOSFET-only voltage reference is realized in this paper which only requires three branches in the core. With the unique characteristics of a self-biased current source, one diode-connected PMOS is adopted to achieve a CTAT voltage with shrunken TC, PTAT voltage generator, and weighted summation at the same time. What is more, the proposed structure is only constructed by MOSFETs, and the generated reference voltage is proportional to the delta threshold voltage. Therefore, the proposed voltage reference is more suitable for low power consumption applications with nanoscale technology, which can be further extended to more advanced technologies.
PSRR of Proposed Voltage Reference
With the help of the proposed self-biased current source, the output node of the current generator part, B, can track the small-signal variation of the supply voltage, which is beneficial for the PSRR improvement of the whole voltage reference.
For VDS > 4VT, the exponential term in Eq. (23) is very large. This makes the PSRR performance to be greatly enhanced with VDS,MP3 increasing. In the proposed design, the minimum VDS,MP3 is over 200 mV, which means the change in the supply voltage has little effect on the VREF. Thus, the proposed structure has a good PSRR performance.
Results and Discussion
Performance summary and comparison
Min. VDD (V)
Temp. range (°C)
− 30 to 80
− 40 to 120
− 40 to 125
− 40 to 85
PSRR (dB) @100 Hz
A resistorless low-power voltage reference with high PSRR is presented in this paper, which is suitable for nanoscale applications and can be extended to more advanced process. With the help of self-biased current source based on MOSFET voltage divider, the required CTAT voltage, PTAT voltage, and weighted summation can be simultaneously realized in a compacted structure. What is more, a delta threshold voltage is chosen as the CTAT voltage, which has a greatly reduced negative TC. This also makes the required value of PTAT voltage to be shrunken. Therefore, the supply voltage and current consumption can be brought down. All the parts are only constructed by MOSFETs, which has priority in power-sensitive highly integrated applications, such as SOC.
This work was supported by the National Science Foundation of China under Grant No. 61674025 and No. 61306035, the Fundamental Research Funds for the Central Universities under Grant No. ZYGX2016J056, and Open Projects of Sichuan Key Laboratory of Meteorological Information and Signal Processing under Grant No. QXXCSYS201504 and No. QXXCSYS201603.
Availability of Data and Materials
All data generated or analyzed during this study are included in this published article.
ZZ proposed the novel structure and was a major contributor in writing the manuscript. JC improved the design of the circuit. YW verified the theory with a simulation. The others authors offered comments and revised the manuscript. All authors read and approved the final manuscript.
The authors declare that they have no competing interests.
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
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