Advertisement

Nanoscale Research Letters

, 14:15 | Cite as

High mobility Ge pMOSFETs with amorphous Si passivation: impact of surface orientation

  • Huan Liu
  • Genquan HanEmail author
  • Yan Liu
  • Xiaosheng Tang
  • Jingchen Yang
  • Yue Hao
Open Access
Nano Express
  • 191 Downloads

Abstract

We report the amorphous Si passivation of Ge pMOSFETs fabricated on (001)-, (011)-, and (111)-orientated surfaces for advanced CMOS and thin film transistor applications. Amorphous Si passivation of Ge is carried out by magnetron sputtering at room temperature. With the fixed thickness of Si tSi, (001)-oriented Ge pMOSFETs achieve the higher on-state current ION and effective hole mobility μeff compared to the devices on other orientations. At an inversion charge density Qinv of 3.5 × 1012 cm−2, Ge(001) transistors with 0.9 nm tSi demonstrate a peak μeff of 278 cm2/V × s, which is 2.97 times higher than the Si universal mobility. With the decreasing of tSi, ION of Ge transistors increases due to the reduction of capacitive effective thickness, but subthreshold swing and leakage floor characteristics are degraded attributed to the increasing of midgap Dit.

Keywords

Germanium MOSFET Amorphous Si passivation Mobility Surface orientation 

Abbreviations

ALD

Atomic layer deposition

BF2+

Boron fluoride ion

CET

Capacitive effective thickness

Ge

Germanium

GeOx

Germanium oxide

HF

Hydrofluoric acid

HfO2

Hafnium dioxide

HRTEM

High-resolution transmission electron microscope

IL

Interfacial layer

MOSFETs

Metal-oxide-semiconductor field-effect transistors

Ni

Nickel

Si

Silicon

SS

Subthreshold swing

TaN

Tantalum nitride

TDMAHf

Tetrakis (dimethylamido) hafnium

Background

Germanium (Ge) has been attracting tremendous research interests for advanced CMOS and thin film transistor applications due to its higher hole mobility and lower thermal budget processing compared to Si [1, 2, 3, 4, 5, 6]. To achieve the high channel mobility, the surface passivation process leading to a high interface quality is required before gate stack formation. Several surface passivation techniques have been developed to deliver the carrier mobility benefits in Ge metal-oxide-semiconductor field-effect transistors (MOSFETs) [1, 2, 7, 8, 9, 10]. Among these techniques, a silicon (Si) cap passivated on Ge has been the hotspot in recent years, due to its advantages of effective suppressing of interface states and good thermal stability and reliability [11]. Formation of Si passivation cap has been widely studied using chemical vapor deposition (CVD) with precursors of SiH4 [1], Si2H6 [4], Si3H8 [12], and E-beam evaporation [13]. Although CVD method could provide the more uniform passivation layer over physical vapor deposition (PVD), its passivation rate has the strong correlation in channel surface orientation and the process temperature. PVD technique could provide the improved passivation rate even at room temperature, which has the advantages of low thermal budget and low cost, making it more suitable for the thin film transistors and back-end-of-line 3D integration applications. In this letter, we fabricated high mobility Ge pMOSFETs on (001)-, (011)-, and (111)-oriented surfaces utilizing amorphous Si passivation by magnetron sputtering. Significantly improved effective hole mobility μeff is achieved in Ge transistors compared to the Si universal mobility. Impacts of surface orientation and thickness of amorphous Si tSi on the boosting effect of amorphous Si passivation on μeff are studied.

Methods

Figure 1a shows the key process steps for fabricating Ge pMOSFETs on (001)-, (011)-, and (111)-oriented surfaces. After pre-gate cleaning in diluted HF (1:50) solution, ultrathin amorphous Si passivation layer was deposited on n-Ge substrates by magnetron sputtering at a target power of 50 W. Three passivation durations of 60 s, 80 s, and 100 s were used corresponding to the deposition of 0.5, 0.7, and 0.9 nm tsi, respectively. After that, a 5-nm thick HfO2 gate dielectric was deposited at 250 °C by atomic layer deposition using TDMAHf and H2O as precursors of Hf and O, respectively. A 50-nm TaN gate electrode was deposited by reactive sputtering. Next, the gate electrode was patterned and etched, which was followed by BF2+ implantation into source/drain (S/D) regions at 30 KeV with a dose of 1 × 1015 cm− 2. Non-self-aligned S/D metals of 15-nm nickel were formed by lift-off process. Finally, rapid thermal annealing at 400 °C was carried out for dopant activation and S/D metallization. Figure 1b shows the cross-sectional schematic of the Ge pMOSFET with Si/SiO2 interfacial layer (IL). Figure 1c shows top-view microscope image of a fabricated Ge pMOSFET.
Fig. 1

a Process sequence showing the key steps employed to fabricate the Ge pMOSFETs with different tSi. b Cross-sectional schematic of a Ge pMOSFET with SiO2 IL. c Top-view microscope image of a fabricated Ge pMOSFET

Figure 2a, b shows the transmission electron microscope (TEM) images of the high-κ/metal gate stack with SiO2/Si interfacial layer (IL) on Ge(001) channel with tSi of 0.5 and 0.9 nm, respectively. Insets show the high-resolution TEM (HRTEM) images of the samples. For the device with a tSi of 0.5 nm, amorphous Si layer was completely oxidized, while for the device with 0.9 nm tSi, about two Si monolayers remained after the subsequent annealing steps.
Fig. 2

Cross-sectional TEM images of Ge pMOSFET gate stacks with a 0.5 nm tSi and b 0.9 nm tSi. HRTEM images in insets show that Si/SiO2 IL is formed between HfO2 and Ge channel

Results and discussion

Figure 3a plots the measured IDS-VGS and IG-VGS curves of the typical Ge pMOSFETs on (001)-, (011)-, and (111)-oriented surfaces with 0.9 nm tSi, which show the excellent transfer characteristics. All transistors have a gate length LG of 3 μm and a gate width W of 100 μm. The channel direction is [110] for all the orientations. The IDS-VDS curves of the devices measured at different gate overdrive VGS-VTH are shown in Fig. 3b. Here, threshold voltage VTH is defined as the VGS at IDS of 10−7 A/μm. It is observed that Ge(001) pMOSFET achieves the higher drive current ION compared to the transistors on (011) and (111) surfaces at the fixed VGS-VTH. Later, we will show that this is attributed to the fact that Ge(001) pMOSFETs have a higher effective hole mobility μeff in comparison with the devices on the other two surface orientations. We perform a comprehensive comparison of electrical performance for the devices with the fixed tSi of 0.9 nm, including ION, leakage floor Ileak, subthreshold swing (SS), and VTH characteristics. Ileak is defined as the minimum IDS at VDS of − 0.05 V. Figure 4a presents the statistical plot of the ION for Ge pMOSFETs on various orientations, and ION was defined as IDS at a VDS of − 0.5 V and a VGS-VTH of − 0.8 V. All the transistors in this plot have the LG of 3 μm and W of 100 μm. (001)-oriented devices exhibit the improved mean ION as compared to those on (011) and (111) orientations, which is attributed to the higher μeff. Figure 4b compares the Ileak for the devices, showing that Ge(001) transistors have the lowest Ileak of them, and Ge(011) pMOSFETs have the lower Ileak than (111)-oriented devices. It should be noted that the Ileak is determined by the reverse current of the p+/n junction in drain region, which is affected by the background n-type doping concentration in Ge substrate and activation of the implanted p+ dopants. The n-type doping concentrations in the wafers with various orientations are not exactly the same. The surface orientation affects the dopant activation rate and recrystallization quality of S/D regions. Furthermore, although the IG is lower than IDS before the turn-on of the transistors, it would influence the Ileak. Similarly, (001)-oriented Ge pMOSFETs demonstrate the improved SS characteristics in comparison with other two orientations, which is due to that transistors on (001) surface have the lower midgap density of interface state Dit compared to the other devices. Figure 4d shows that the devices on different orientations have the different VTH. Based on the results in Fig. 4, it is concluded that, with the fixed tSi of 0.9 nm, (001)-oriented Ge pMOSFETs obtain the best electrical characteristics.
Fig. 3

a Measured IDS-VGS and IG-VGS curves of (001)-, (011)-, and (111)-oriented Ge pMOSFETs with 0.9 nm tSi showing the excellent transfer characteristics. b IDS-VDS curves measured at different VGS-VTH for the devices

Fig. 4

Comparison of a ION, b Ileak, c SS, and d VTH for (001)-, (011)-, and (111)-oriented Ge pMOSFETs with a tSi of 0.9 nm

The thicknesses of Si/SiO2 IL in transistors with 0.9 nm tSi on different surface orientations are studied by using inversion capacitance Cinv versus VGS measurement, as shown in Fig. 5. Forward and reverse sweeping measurements exhibit the negligibly small hysteresis in the devices. The transistors exhibit the similar magnitude of Cinv, ~ 1.56 μF/cm2, corresponding to the capacitive effective thickness (CET) of 2.2 nm. Figure 5b show the statistical results of saturated Cinv for the devices, which demonstrate the very small difference in Cinv in the transistors on different surface orientations. This indicates that the passivation rate of amorphous Si by magnetron sputtering is independent of the surface orientation. The rule of left-right shifts of the Cinv-VGS curves is well consistent with that of VTH for the devices in Fig. 4d, which might be induced by the slightly different doping concentration in different orientation substrates.
Fig. 5

a Comparison of inversion Cinv-VGS curves among the Ge pMOSFETs with 0.9 nm tSi on different orientations. Both forward and reverse sweeping are shown. b Statistical plots for the saturated Cinv of the devices showing the negligible differences in Cinv in the inversion regime

Figure 6 compares the mobility characteristics of the transistors with 0.9 nm tSi on various surface orientations. The μeff was extracted using a total resistance slope-based method [14]. Ge(001) pMOSFETs exhibit the much higher channel mobility compared to the devices on (011) and (111) orientations. Transistors on (001) substrate achieve a peak μeff of 278 cm2/V·s at an inversion charge density Qinv of ~ 3.5 × 1012 cm−2, which is 2.97 times higher than the Si universal mobility. Surface roughness at the Si/Ge interface and density of interface states (Dit) can affect μeff of the devices at high inversion carrier density. It is unlikely that the commercially purchased Ge wafers with various surface orientations have the obvious difference in surface roughness. Therefore, it is speculated that the mobility enhancement in (001)-oriented devices is mainly due to reduced carrier scattering contributed by interface states. In this work, we evaluate the midgap Dit of the devices, and with the fixed tSi of 0.9 nm, the (001)-oriented Ge pMOSFETs indeed have the lower midgap Dit compared to the other orientations.
Fig. 6

Plot of μeff versus Qinv for Ge pMOSFETs with 0.9 nm tSi on (001)-, (011)-, and (111)-oriented substrates. Ge(001) pMOSFETs achieve the 2.97 times enhancement in μeff at a Qinv of 3.5 × 1012 cm−2 as compared to the Si universal mobility. The μeff was extracted using a total resistance slope-based method [17]

The impact of tSi on the electrical performance of Ge pMOSFETs is also investigated. Figure 7a, b present the measured IDS-VGS and IDS-VDS curves, respectively, of the (111)-oriented Ge pMOSFETs with tSi of 0.5, 0.7, and 0.9 nm at a VDS of − 0.05 and − 0.5 V. The transistors have a LG of 1.5 μm. It is observed that Ge pMOSFETs with 0.9 nm tSi exhibit improved transfer characteristics compared to the devices with thinner tSi, but ION of the device decreases with the increasing of tSi. At VDS of − 1.5 V and VGS-VTH of − 0.8 V, Ge(111) pMOSFET with 0.5 nm tSi demonstrates a 32% improvement in ION compared to the device with 0.9 nm tSi. Figure 8 plots the statistical results of ION, Ileak, SS, and VTH of the Ge pMOSFETs on (111)-orientation with different tSi. From Fig. 8a, we see that transistors with 0.5 nm tSi achieve the improved ION in comparison with the devices with thicker tSi, which is due to the transistor with 0.5 nm tSi that has a smaller CET, leading to a higher Cinv. It is noticed that Ileak decreases with the increasing of tSi (Fig. 8b), and transistors with 0.5 nm tSi has the inferior SS characteristics to those of the devices with 0.7 and 0.9 nm amorphous Si passivation layer (Fig. 8c). This might be due to those transistors with 0.5 nm tSi having a higher midgap Dit. The relation between SS and midgap Dit of Ge pMOSFET can be expressed by SS = ln(10) ⋅ (kT/q) ⋅ [1 + (Cit + Cd)/Cox], where Cox, Cd, and Cit are oxide capacitance, depletion-layer capacitance, and capacitance from interface traps, respectively. Cit can be calculated by q × Dit, were Dit is the interface trap density. Although transistor with 0.5 nm tSi has the larger Cox compared to the other two devices, its higher midgap Dit can lead to the inferior SS to the devices with the thicker tSi. The surface passivation will also affect the Ileak from drain to source. With the sweeping of VGS from position to negative, the channel transfers from accumulation mode to inversion mode. However, if the Dit is high, some points in channel surface are pinned by the interface traps, and the leakage paths can be formed, increasing Ileak from drain to source. As shown in Fig. 8d, Ge(111) pMOSFETs show the shift of VTH to negative VGS direction with the increasing of tSi, which is attributed to the increased CET. In addition, the density of traps in the lower bandgap half seems to increase for the thinner tSi, which might lead to the shift of VTH [2].
Fig. 7

a IDS-VGS and IG-VGS and b IDS-VDS curves of Ge(111) pMOSFETs with various tSi. Transistor with 0.5 nm tSi exhibits a 32% improvement in ION compared to the device with 0.9 nm tSi at VDS of − 1.5 V and VGS-VTH of − 0.8 V

Fig. 8

Comparison of a ION, b Ileak, c SS, and d VTH for (111)-oriented Ge pMOSFETs with 0.5, 0.7, and 0.9 nm tSi showing that transistors with 0.5 nm tSi have the better ION, but worse SS and Ileak characteristics in comparison with devices with thicker tSi

Figure 9a shows the Cinv as a function of VGS curves for the Ge pMOSFETs on (111)-oriented surface with tSi of 0.5, 0.7, and 0.9 nm measured at a frequency of 300 kHz. The CET values in inversion regions are extracted to be 1.8, 1.9, and 2.2 nm for the devices with 0.5, 0.7, and 0.9 nm tsi, respectively. μeff as a function of Qinv characteristics of the devices are extracted and shown in Fig. 9b. The (111)-oriented Ge pMOSFET with 0.7 nm tsi achieves the highest peak mobility of 229 cm2/V s, which is 2.27 times higher compared to the Si universal mobility. It should be noted that the devices with 0.5 nm tSi exhibit a significantly improved μeff over the transistors with thicker tSi at high Qinv (e.g. 1013 cm−2). This also leads to the higher ION at high VGS-VTH in the devices with 0.5 nm tSi compared to the devices with 0.7 and 0.9 nm tSi. The μeff at high Qinv decreases as tSi increases from 0.5 nm to 0.7~0.9 nm, which is attributed to the fact that the larger surface roughness leads to the stronger surface roughness scattering of the carriers. During the passivation of Ge surface using magnetron sputtering at room temperature, the diffusion of surface atoms is greatly suppressed. So with the increasing of tSi, the surface roughness is larger, which can be observed from the HRTEM images in Fig. 2.
Fig. 9

a Cinv-VG characteristics measured at 300 kHz for (111)-oriented devices with 0.5, 0.7, and 0.9 nm tSi. b μeff as a function of Qinv for Ge pMOSFETs [17]

In Fig. 10, we benchmark the μeff of the Ge pMOSFETs in this work with those of the reported relaxed Ge transistors with Si by E-beam evaporation, SiH4, Si2H6, and Si3H8 passivation. Compared to the amorphous Si by E-beam evaporation in Ref. [15], Ge pMOSFETs in this work exhibit the significantly improved μeff. It is seen that, at the similar CET, Ge pMOSFETs utilizing amorphous Si passivation by magnetron sputtering have the lower μeff in comparison with the devices with Si2H6 passivation. The process of passivation using amorphous Si needs to be further optimized to enhance the carrier mobility.
Fig. 10

a μeff for the Ge pMOSFETs in this work vs. the published results for relaxed Ge pMOSFETs. b, c Benchmarking of μeff extracted at Qinv = 5 × 1012 and 1 × 1013 cm−2, respectively, of the Ge pMOSFETs with the different CET values [18, 19]

Ge pMOSFETs with the different tSi on (001)-oriented surface are also characterized. Figure 11a, b illustrate the measured IDS-VGS and IDS-VDS curves, respectively, of a pair of Ge(001) pMOSFETs with 0.5 and 0.9 nm tSi. Similar to the (111)-oriented devices, Ge(001) pMOSFET with 0.5 nm tSi obtains the improvement in ION but the degradation in Ileak compared to the transistor with 0.9 nm tSi.
Fig. 11

a Measured IDS-VGS and IG-VGS curves of (001)-oriented Ge pMOSFETs with 0.5 and 0.9 nm tSi. b IDS-VGS curves of the devices

The midgap Dit characteristics of Ge pMOSFETs are studied by the method in [16], and values of Dit are calculated by Dit = [SSlog(e)/(kT/q) − 1]CG/q, [16] where q is the electron charge, k is Boltzmann’s constant, T is the absolute temperature, and CG is the measured gate capacitance per unit area. Figure 12 shows Dit as a function of the thickness of amorphous Si with various Ge surface orientations. For (111)-oriented surface, a device with 0.7-nm tsi has the lowest Dit value. With the 0.9 nm tSi, (001)-oriented device has the lower Dit compared to the transistors on other orientations.
Fig. 12

Dit versus the thickness of amorphous Si with various Ge surface orientations

Finally, we compare the key electrical characteristics of Ge pMOSFETs on the different orientations in Table 1. With a fixed tSi, Ge(001) pMOSFET has the improved electrical performance compared to the other two orientations. The drive current can be enhanced by reducing the tSi from 0.9 nm to 0.5 nm, which is due to that the thinner tSi provides a significantly reduced CET without causing degradation in μeff.
Table 1

Key electrical performance of Ge pMOSFETs on the different orientations

Substrate orientation

tSi (nm)

CET (nm)

Midgap Dit (cm− 2 eV − 1)

SS (mV/decade)

ION@VDS = − 0.5 V, VGS-VTH = − 0.8 V

(LG = 3 μm)

(μA/μm)

Ileak (nA/μm)

μeff@

Qinv = 5 × 1012 cm− 2

(cm2/V × s)

(001)

0.9

2.2

9.3 × 1012

115

17.2

1.6

273

(011)

0.9

2.2

1.4 × 1013

159

15.1

5.5

240

(111)

0.9

2.2

2.1 × 1013

187

13.2

10.7

203

(111)

0.7

1.9

1.8 × 1013

166

17.3

12.3

218

(111)

0.5

1.8

2.7 × 1013

209

20.3

19.8

212

Conclusions

Ge pMOSFET passivated by amorphous Si are demonstrated on (001)-, (011)-, and (111)-oriented substrate. With a tSi of 0.9 nm, the improved ION and SS characteristics are obtained in (001)-oriented Ge pMOSFETs in comparison with the devices on (011) and (111) orientations, due to the higher μeff and lower midgap Dit. Ge(001) pMOSFETs with 0.9 nm tSi achieve a peak mobility of 278 cm2/V s at a Qinv of 3.5 × 1012 cm−2, which is 2.97 times higher than the Si universal mobility. It is demonstrated that ION of the devices is improved with the decreasing of tSi due to the reduction of CET. But Ge pMOSFETs with thicker tSi exhibit the superior subthreshold swing and leakage floor, owing to that midgap Dit can be reduced by increasing tSi.

Notes

Acknowledgements

Not applicable.

Funding

The authors acknowledge support from the National Natural Science Foundation of China under Grant No. 61534004, 61604112, and 61622405.

Availability of data and materials

The datasets supporting the conclusions of this article are included within the article.

Authors’ contributions

HL carried out the experiments and drafted the manuscript. GQH and YL supported the study and helped to revise the manuscript. XST and JCY helped to carry out the measurements. YH provided constructive advice in the drafting. All the authors read and approved the final manuscript.

Competing interests

The authors declare that they have no competing interests.

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

References

  1. 1.
    Wu N, Zhang Q, Zhu C, Chan DSH, Du A, Balasubramanian N, Li MF, Chin A, Sin JKO, Kwong DL (2004) A TaN-HfO2-Ge pMOSFETs with novel SiH4 surface passivation. IEEE Electron Device Lett 25:631–633CrossRefGoogle Scholar
  2. 2.
    Mitard J, Jaeger BD, Leys FE, Hellings G, Martens K, Eneman G, Brunco DP, Loo R, Lin JC, Shamiryan D, Vandeweyer T, Winderickx G, Vrancken E, Yu CH, Meyer KD, Caymax M, Pantisano L, Meuris M, Heyns MM (2008) Record ION/IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability. In: IEDM Tech Dig, pp 873–876  https://doi.org/10.1109/IEDM.2008.4796837 Google Scholar
  3. 3.
    Vincent B, Loo R, Vandervorst W, Delmotte J, Douhard B, Valev VK, Vanbel M, Verbiest T, Rip J, Brijs B, Conard T, Claypool C, Takeuchi S, Zaima S, Mitard J, Jaeger BD, Dekoster J, Caymax M (2011) Si passivation for Ge pMOSFETs: impact of Si cap growth conditions. Solid State Electron 60:116–121CrossRefGoogle Scholar
  4. 4.
    Liu Y, Yan J, Han GQ, Wang HJ, Liu MS, Zhang CF, Cheng BW, Hao Y (2014) Strained Ge0.96Sn0.04 P-channel MOSFETs with in situ low temperature Si2H6 surface passivation. In: ISTDM Tech Dig, pp 107–108  https://doi.org/10.1109/ISTDM.2014.6874637 Google Scholar
  5. 5.
    Liao CY, Chen SH, Huang WH, Shen CH, Shieh JM, Cheng HC (2018) High-performance recessed-channel germanium thin-film transistors via excimer laser crystallization. IEEE Electron Device Lett 39:367–370CrossRefGoogle Scholar
  6. 6.
    Sadoh T, Kamizuru H, Kenjo A, Miyao M (2006) Low-temperature formation (< 500 °C) of poly-Ge thin-film transistor with NiGe Schottky source/drain. Appl Phys Lett 89:192–114Google Scholar
  7. 7.
    Xie R, Phung TH, He W, Sun Z, Yu M, Cheng Z, Zhu C (2008) High mobility high-k/Ge pMOSFETs with 1 nm EOT-new concept on interface engineering and interface characterization. In: IEDM Tech Dig, pp 1–4  https://doi.org/10.1109/IEDM.2008.4796703 Google Scholar
  8. 8.
    Takagi S, Noguchi M, Kim M, Kim SH, Chang CY, Yokoyama M, Nishi K, Zhang R, Ke M, Takenaka M (2016) III-V/Ge MOS device technologies for low power integrated systems. Solid State Electron 125:82–102CrossRefGoogle Scholar
  9. 9.
    Kuzum D, Pethe AJ, Krishnamohan T, Saraswat KC (2009) Ge (100) and (111) N-and P-FETs with high mobility and low-T mobility characterization. IEEE Trans Electron Devices 56:648–655CrossRefGoogle Scholar
  10. 10.
    Hashemi P, Hoyt JL (2012) High hole-mobility strained-Ge/Si0.6Ge0.4 p-MOSFETs with high-K metal gate: role of strained-Si cap thickness. IEEE Electron Device Lett 33:173–175CrossRefGoogle Scholar
  11. 11.
    Kaczer B, Franco J, Mitard J, Roussel PJ, Veloso A, Groeseneken G (2009) Improvement in NBTI reliability of Si-passivated Ge/high-k/metal-gate pFETs. Microelectronic Eng 86:1582–1584CrossRefGoogle Scholar
  12. 12.
    Mitard J, Martens K, Jaeger BD, Franco J, Shea C, Plourde C, Leys FE, Loo R, Hellings G, Eneman G, Wang WE, Lin JC, Kaczer B, DeMeyer K, Hoffmann T, DeGendt S, Caymax M, Meuris M, Heyns MM (2009) Impact of epi-Si growth temperature on Ge-pFET performance. In: European Solid State Device Research Conference, pp 411–414  https://doi.org/10.1109/ESSDERC.2009.5331351 Google Scholar
  13. 13.
    Chen WB, Chin A (2010) High performance of Ge nMOSFETs using SiO2 interfacial layer and TiLaO gate dielectric. IEEE Electron Device Lett 31:80–82CrossRefGoogle Scholar
  14. 14.
    Niu G, Cressler JD, Mathew SJ, Subbanna S (1999) A total resistance slope-based effective channel mobility extraction method for deep submicrometer CMOS technology. IEEE Trans Electron Devices 46:1912–1914CrossRefGoogle Scholar
  15. 15.
    Lee CH, Nishimura T, Tabata T, Wang SK, Nagashio K, Kita K, Toriumi A (2010) Ge MOSFETs performance: impact of Ge interface passivation. In: IEDM Tech Dig, pp 416–419  https://doi.org/10.1109/IEDM.2010.5703384 Google Scholar
  16. 16.
    Greve DW (1998) Field effect devices and application: devices for portable, low-power, and imaging systems, 1st edn. Prentice-Hall, EnglewoodGoogle Scholar
  17. 17.
    Takagi S, Twase M, Toriumi A (1998) On the universality of inversion-layer mobility in n-and p-channel MOSFETs. In: IEDM Tech Dig, pp 398–401  https://doi.org/10.1109/IEDM.1988.32840 Google Scholar
  18. 18.
    Pillarisetty R, Chu-Kung B, Corcoran S, Dewey G, Kavalieros J, Kennel H, Kotlyar R, Le V, Lionberger D, Metz M, Mukherjee N, Nah J, Rachmady W, Radosavljevic M, Shah U, Taft S, Then H, Zelick N, Chau R (2010) High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III-V CMOS architecture. In: IEDM Tech. Dig, pp 150–153  https://doi.org/10.1109/IEDM.2010.5703312 Google Scholar
  19. 19.
    Mitard J, Witters L, Vincent B, Franco J, Eavia P, Hikavyy A, Eneman G, Loo R, Brunco DP, Kabir N, Bender H, Sebaai F, Vos R, Mertens P, Milenin A, Vecchio E, Ragnarsson L-Å, Collaert N, Thean A (2013) First demonstration of strained Ge-in-STI IFQW pFETs featuring raised SiGe75% S/D, replacement metal gate and germanided local interconnects. In: VLSIT Dig, pp T20–T21Google Scholar

Copyright information

© The Author(s). 2019

Open AccessThis article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.

Authors and Affiliations

  1. 1.State Key Discipline Laboratory of Wide Band Gap Semiconductor Technology, School of MicroelectronicsXidian UniversityXi’anChina
  2. 2.College of Optoelectronic EngineeringChongqing UniversityChongqingChina

Personalised recommendations