Graphene-Based Nanoscale Vacuum Channel Transistor
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We report the fabrication and electrical performance of nanoscale vacuum channel transistor (NVCT) based on graphene. Ninety-nanometer-width vacuum nano-channel could be precisely fabricated with standard electron beam lithography process. The optimization and treatment of surface damage and adhesive residue on graphene are carried out by ultrasonic cleaning and thermal annealing. Additionally, in situ electric characteristics are directly performed inside a vacuum chamber of scanning electron microscope (SEM) with the nanomanipulator. By modulating the gate voltage, the NVCT could be switched from off-state to on-state, exhibiting an on/off current ratio up to 102 with low working voltages (< 20 V) and leakage current (< 0.5 nA). Furthermore, the nanoscale vacuum channel could enable to scale down the size of vacuum devices with high integration, making NVCT a promising candidate for high speed applications.
KeywordsNanoscale vacuum channel Graphene In situ measurement
Chemical vapor deposition
Electron beam lithography
Field effect transistor
Focused ion beam
Nanoscale vacuum channel transistor
Plasma-enhanced chemical vapor deposition
Scanning electron microscope
As the traditional Si-based technology gradually reaches the minimize limitation, many efforts have been made in the novel nanostructures or low-dimensional materials [1, 2, 3, 4, 5, 6, 7]. Among these prominent issues, transistors composed of nanoscale vacuum channels or known as the nanogap have been steadily attracting attentions [8, 9, 10]. Distinct from the early vacuum tubes with high-power consumption and difficulty for high integration, the nanogap structures are more prospective for the modern nanoelectronics. For conventional field effect transistors (FETs), the carriers may collide with the optical and acoustic phonons during the transport. Also, intrinsic graphene-based FETs were found to have an on–off current ratio less than 10 due to the lack of a bandgap, which are not suitable for modern integrated logic circuits. Intrinsically, electrons could ballistically travel through the nanoscale vacuum channel while suffering from collision or scattering in the semiconductors. And the vacuum nano-devices could be compatible with standard silicon process and combine the advantages of ballistic transport with miniaturization and integration. Thus, the nanoscale vacuum channel transistors (NVCTs) may output high frequency [9, 11], on/off ratio , or fast temporal response  with low working voltage. More importantly, the NVCT is proved to retain the advantages of the traditional vacuum tubes that operate normally in the extreme conditions, like exposure of ionizing radiation or high temperature . The development of manufacturing technology can open up enormous opportunities for creating nanoscale vacuum channel, which might be compatible with modern integrated circuit (IC).
As a result, many attempts have been made to downscale the vacuum channel into nanogap and construct three terminal junctions. For instance, the vertical structure was widely utilized in the traditional vacuum electronic devices [14, 15]. Researchers have proposed different types of vertical NVCTs, where the electrons could emit directly out of plane, e.g., the slit-type vacuum transistor , or the Spindt-type NVCT . However, the vertical structure could hardly be compatible with CMOS process. Compared with up–down structure, the planar NVCT are more prospective for future integration as the nanogap is variable with mask layout, including electron beam lithography (EBL) , focused ion beam (FIB) , or nanoimprinting . Recently, planar-type vacuum transistors with nanogap channel have been fabricated with traditional semiconductor processing. Meyyappan et al. demonstrated a back-gate vacuum nano-channel transistor with standard silicon semiconductor processing, showing high-frequency switching characteristics with negligible leakage current . In order to enhance the gate controllability, they further fabricated a surround-gate NVCT consists of sub-50-nm vacuum channel, and the device was proven to stand against ionizing radiation (proton and Gamma ray) and high temperature (200 °C) . Wei et al. successfully fabricated a graphene-based vacuum transistor with better electrical performance than those graphene-based solid-state transistors. With superior on/off current ratio and low working voltages, the graphene NVCT are expected to be applied in severe environments such as electromagnetic radiation or extreme temperature . Our previous work also precisely fabricated sub-30 nm aligned nanogap arrays with a well-controlled process . The experimental results above indicate that the vacuum nano-devices, composed of the nanoscale vacuum channel, have the advantages of high response speed, low operating voltage, and superior switching performance and, more importantly, could be compatible with standard silicon process and combine the advantages of ballistic transport with miniaturization and integration. In particular, the nano-channel that smaller than the mean free path of electron can behave as vacuum without scattering or collision. Thus, the NVCT may function in low vacuum environment or even atmosphere, paving the way for a new generation of high performance, high-speed and low-cost vacuum electronic devices.
Here, we report on the fabrication of a graphene-based NVCT using optimized wet transfer method and standard EBL processing. Vacuum nano-channel of 90 nm has been achieved with a back-gate structure, which could modulate the electric field of emitting area and the electron transmission through emitter to collector. In situ electric characteristics are performed in the vacuum chamber of scanning electron microscope (SEM) with a nanomanipulator, showing the basic functionality with high on/off current ratio, low work voltage, and leakage current. Importantly, we believe that further downscaling of the channel size could fulfill high speed, high reliability, and low-cost applications for modern electronics.
In this report, large-scale graphene was directly grown on the Cu foil by thermal chemical vapor deposition (CVD) at 1020 °C with CH4 (20 sccm) and H2 (40 sccm) . Among various transfer techniques for CVD-grown graphene, the mainstream method is the chemical transfer using PMMA as a support layer. Firstly, a PMMA layer was spin-coated on the graphene/Cu film and baked at 100 °C for 5 min to solidify PMMA. After etching in the FeCl3:HCl:H2O solution (molar mass ratio of 1:1:1) for 90 min, the remaining PMMA/graphene film was transferred and soaked in the deionized water for 5 min. This cleaning operation was repeated four or five times to fully remove the etching solution residue. Then, the PMMA/graphene film was transferred to the SiO2/Si substrates and dried at 100 °C for 5 min, removing the residual water between the membrane and substrate. Lastly, the sample was soaked in the acetone solution for an hour to remove the PMMA support layer.
Figure 2a clearly shows the optical photograph of the produced 2 cm × 2 cm graphene film on SiO2/Si substrate, indicating the excellent transparence of graphene. The graphene/SiO2 was characterized by field emission scanning electron microscope (Quanta 200 FEI), as is shown in Fig. 2b. The SEM image demonstrates that the graphene was continuous and uniformly transferred onto the substrate with few cracks or winkles. Moreover, Raman spectroscopy (514-nm laser excitation) is commonly used to evaluate the quality of the transferred graphene. Figure 2c shows the typical Raman spectrum of the graphene on SiO2/Si substrate. With unconspicuous D peak located at 1349 cm−1, the G and 2D peaks could be clearly observed at 1587 and 2685 cm−1 with a 2D/G ratio of 2.19. The low intensity of the D peak demonstrates that few additional defects were generated during the transfer process. The 2D peak is narrow with ratio IG/I2D below 0.5, which indicates the basic features of single-layer graphene. The Raman spectrum results show high quality and continuity of the graphene with our optimized chemical transfer method.
Fabrication of Graphene-Based Nanoscale Vacuum Channel Transistor
Results and Discussion
Figure 5b, c shows the band diagram of graphene-based NVCT at on- and off-states, respectively. Generally, the gate voltage applied at the back-gate could modulate the vacuum barrier between emitter and collector. When the gate voltage is less than the threshold voltage, the barrier is too broad to field tunneling for low-energy electrons. Also, the electrons might receive scattering by the impurities on the SiO2 surface and trapped to the drawbacks of the emitter. As the gate voltage increases beyond the threshold voltage, the width of the barrier is compressed accordingly. The electrons could overcome the narrowed barrier via the F-N tunneling, leading to the on-state of the NVCT. Moreover, the tunability of graphene energy band by gate voltage may be another contribution, as electrical conductivity of single-layer graphene can be modulated by gate voltage. As the gate voltage increases, the Fermi level EF shift to the conduction band, thus, enhance the electron density of the graphene surface and improve the emission current.
To rule out the possibility of electron emission through the insulator, we also detect the leakage current during the measurement. Low and negligible leakage current (less than 0.5 nA) is observed, owing to the 100-nm thick SiO2 insulator. With a back-gate structure, however, the insulator plays a crucial role in the device. A thin insulator could enhance the modulation ability of back-gate while the insulator should be strong enough to avoid breakdown. As a result, optimizing the insulator material to decrease the thickness and improve the breakdown strength, e.g., utilizing Al2O3 or HfO2 as the high-k gate insulator [26, 27, 28, 29, 30, 31], could indeed enhance the electric performance of the NVCT. Besides, the stability test of the NVCT at different vacuum degrees is shown in Fig. 6d with a fixed collector and gate voltage set as 7.5 V and 15 V, respectively. With the high thermal conductivity of graphene, the decrease of emission current induced by Joule heating is weakened, showing no obvious degradation and fluctuation at a vacuum degree of ~ 10−4 Pa. However, a slowly current reduction is observed in low vacuum (~ 10−1 Pa). The inset clearly exhibits the fracture and cracks on the graphene surface after stability test. It is supposed that the Joule heat aggregates at the graphene emitter and damages the surface morphology, leading to the emission current degradation in low vacuum [32, 33]. We hope that it could be solved in the further work, so that widens the application scope and occasion of the graphene-based NVCT.
Comparison of the performances of nanoscale vacuum channel transistors
Channel width (nm)
Operating voltage (V)
Working current (nA)
Gate current (nA)
Vertical graphene-based vacuum transistor 
Planar back-gate vacuum channel transistor 
4 × 104
Gate-all-around vacuum channel transistor 
In conclusion, a graphene-based NVCT was successfully fabricated with standard CMOS process. We utilized the ultrasound to clean the SiO2/Si substrates with a post-annealing process based on the traditional wet transfer method that a 2 cm × 2 cm graphene membrane could be continuously transferred to the substrate. The electrical properties of NVCT were investigated. By modulating the gate voltage, the NVCT could be switched from off-state to on-state, exhibiting an on/off current ratio up to 102 with low working voltages (< 20 V) and leakage current (< 0.5 nA). Further improvement of the graphene-based NVCT by structure optimization may pave the way for high speed, high reliability, and low cost applications for modern vacuum nanoelectronics.
This work was supported by the National Natural Science Foundation of China (Grant Nos. 61775035, 61571124) and Natural Science Foundation of Jiangsu Province (Grant Nos. BK20171365, BK20150632).
Availability of Data and Materials
We declared that materials described in the manuscript, including all relevant raw data, will be freely available to any scientist wishing to use them for noncommercial purposes, without breaching participant confidentiality.
All the authors listed are from the Joint International Research Laboratory of Information Display and Visualization, School of Electronic Science and Engineering, Southeast University, Nanjing 210096, China.
ZXB designed the experimental content. XJ wrote the paper, finished the experiments, and analyzed the data. GZY and YWX helped to prepare the samples. WQL revised the paper. All authors read and approved the final manuscript.
The authors declare that they have no competing interests.
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