Analog/RF Performance of T-Shape Gate Dual-Source Tunnel Field-Effect Transistor
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In this paper, a silicon-based T-shape gate dual-source tunnel field-effect transistor (TGTFET) is proposed and investigated by TCAD simulation. As a contrastive study, the structure, characteristic, and analog/RF performance of TGTFET, LTFET, and UTFET are discussed. The gate overlap introduced by T-shape gate can enhance the efficiency of tunneling junction. The dual-source regions in TGTFET can increase the on-state current (ION) by offering a doubled tunneling junction area. In order to further improve the device performance, the n+ pocket is introduced in TGTFET to further increase the band-to-band tunneling rate. Simulation results reveal that the TGTFET’s ION and switching ratio (ION/IOFF) reach 81 μA/μm and 6.7 × 1010 at 1 V gate to source voltage (Vg). The average subthreshold swing of TGTFET (SSavg, from 0 to 0.5 V Vg) reaches 51.5 mV/dec, and the minimum subthreshold swing of TGTFET (SSmin, at 0.1 V Vg) reaches 24.4 mV/dec. Moreover, it is found that TGTFET have strong robustness on drain-induced barrier lowering (DIBL) effect. The effects of doping concentration, geometric dimension, and applied voltage on device performance are investigated in order to create the TGTFET design guideline. Furthermore, the transconductance (gm), output conductance (gds), gate to source capacitance (Cgs), gate to drain capacitance (Cgd), cut-off frequency (fT), and gain bandwidth (GBW) of TGTFET reach 232 μS/μm, 214 μS/μm, 0.7 fF/μm, 3.7 fF/μm, 11.9 GHz, and 2.3 GHz at 0.5 V drain to source voltage (Vd), respectively. Benefiting from the structural advantage, TGTFET obtains better DC/AC characteristics compared to UTFET and LTFET. In conclusion, the considerable good performance makes TGTFET turn into a very attractive choice for the next generation of low-power and analog/RF applications.
KeywordsT-shaped gate Recessed gate Tunnel field-effect transistor (TFET) Analog/RF performance
Gate to drain capacitance
Gate to source capacitance
Height of the channel layer
Height of the gate electrode
Height of the source layer
L-shape gate tunnel field-effect transistor
Doping concentration of n+ drain
Doping concentration of n+ pocket
Doping concentration of p+ source
Doping concentration of p− substrate
T-shape gate dual-source tunnel field-effect transistor
Thickness of the HfO2 gate dielectric
Thickness of n+ pocket
U-shape gate tunnel field-effect transistor
Drain to source voltage
Gate to source voltage
Width of the gate electrode
The scaling down of metal-oxide-semiconductor field-effect transistors (MOSFETs) brings significant improvement in integrated circuit (IC) power consumption, switching characteristic, circuit function, and IC density [1, 2]. But the irreconcilable contradiction between the scaling of the supply voltage and the reduction of the off-state leakage currents (IOFF) will finally result in the unacceptable high power consumption . At the same time, reliability degradation caused by short-channel effects (SCEs) becomes more and more serious [4, 5]. In order to address these problems, it is valid to reduce subthreshold swing (SS) and supply voltage of the devices. Based on the band-to-band tunneling mechanism, tunnel field-effect transistors (TFETs) reach the subthreshold swing (SS) smaller than 60 mV/dec and could effectively reduce the supply voltage [6, 7, 8, 9, 10]. Moreover, due to the existence of the tunneling junction near the source, TFET usually has a small gate to source capacitance (Cgs) [1, 11] which is beneficial to the device frequency performance.
Recent studies show that TFET seems to be a promising candidate for future low-power applications [12, 13, 14, 15, 16] and analog/RF applications [17, 18, 19]. However, due to the small effective tunneling area, the limited tunneling current becomes an inherent disadvantage in conventional P-I-N TFET, which leads to a low on-state operating current (ION). In order to improve the TFET performance, many new structures have been proposed in recent years [20, 21, 22, 23, 24, 25]. Benefiting from the recessed gate, L-shape tunnel field-effect transistor (LTFET) [23, 24] and U-shape tunnel field-effect transistor (UTFET)  have been proposed to obtain high ION with a compact device structure. However, there is still much room for improvement in LTFET and UTFET and needs to spend more effort to study the analog/RF performance of these devices.
In this paper, a T-shape gate dual-source tunnel field-effect transistor (TGTFET) with dual source is put forward and studied by TCAD simulation. The designed TGTFET can double the tunneling junction area compared with LTFET and UTFET. The gate overlap introduced by the designed T-shape gate can enhance the band-to-band tunneling rate (BBT rate). The simulation results show that the proposed TGTFET gains a higher ION (8.1 × 10− 5 A/μm at Vd = 1 V) than the LTFET and UTFET under the same condition. Both of the SSmin (at Vg = 0.1 V) and the SSavg (0~0.5 V Vg) of TGTFET are lower than 60 mV/dec (24.4 mV/dec and 51.5 mV/dec, respectively). TGTFET gains better input/output characteristic (gm = 232 μS/μm, gds = 214 μS/μm) than the UTFET and LTFET. Moreover, the capacitance characteristics of TGTFET, UTFET, and LTFET are discussed in detail. Finally, TGTFET gains better analog/RF performance (fT = 11.9 GHz and GBW = 2.3 GHz) compared to UTFET and LTFET. As a result, TGTFET with considerable good performance can be obtained.The structures of this paper are as follows: the “Methods” section includes the description of the structure and the parameters of TGTFET, LTFET [23, 24], and UTFET  as well as the TCAD simulation methods. The “Results and Discussion” section includes the description of the simulation results. In this section, the mechanism, characteristic, and analog/RF performance of TGTFET are studied and compared with the LTFET and UTFET. The influence of the device parameters on TGTFET is analyzed in detail too. The “Conclusions” section gives a conclusion of this paper.
Parameters of silicon-based TGTFET, UTFET, and LTFET used in simulations are as follows: Hs = 30 nm (height of the source region), Hg = 40 nm (height of the recessed gate), Wg = 6 nm (width of the gate region), Hc = 15 nm (height of the channel region), Tp = 5 nm (thickness of the n+ pocket), ϕ = 4.33 eV (gate work function), Tox = 2 nm (thickness of the HfO2 gate dielectric), NS = 1 × 1020 cm−3 (p+ source doping concentration), ND = 1 × 1019 cm−3 (n+ drain doping concentration), Nsub = 1 × 1017 cm−3 (p− substrate doping concentration), and NP = 5 × 1018 cm−3 (n+ pocket doping concentration). The width coefficient in simulation is default to 1 μm.
Simulations of TGTFET, UTFET, and LTFET are carried out in Silvaco Atlas TCAD tools. Non-local BTBT model is introduced in this simulation to bring the energy band spatial variation into account, which can help to facilitate the accuracy of the BTBT tunneling process. Lombardi mobility model is considered to make the channel mobility more accurate (by considering the surface scattering including the transverse field and doping concentration). Fermi statistics and band gap narrowing model is taken into account to fit the effect of the highly doped regions. Shockley-Read-Hall recombination model is taken into account in this paper, too.
Results and Discussion
Device Mechanism and DC Characteristics with Different Parameters
Analog/RF Performance of TGTFET, UTFET, and LTFET
As a result, the maximum transconductance of TGTFET (232 μS/μm) is about two times larger than that of UTFET (120 μS/μm) and LTFET (110 μS/μm), as shown in Fig. 10. This is benefited from the current gain contributed by dual source and gate overlap.
Due to the advantages on output current, TGTFET gains the highest gds and the minimum Ro of these three devices. Under 1-V gate bias condition, TGTFET obtained the maximum gds of 214 μS/μm and the minimum Ro of 4.6 kΩ/μm under 0.45 V Vd. Under the same gate bias condition, UTFET and LTFET obtained the maximum gds of 113 μS/μm and 105 μS/μm and the minimum Ro of 9.0 kΩ/μm and 9.6 kΩ/μm under 0.4 V Vd.
It can be obtained from the above analysis that the Ro of TFET is influenced by both the tunneling process and the channel electron thermal excitation process. The main physical mechanisms can dominate Ro shifts with Vd variation. Finally, the Ro decreases first and then increases, thus causing the nonlinearity of the output characteristics. Incidentally, through the observation of Fig. 11b, it is easy to find that the output impedance of TGTFET is much smaller than that of the UTFET and LTFET. This is due to the better tunneling efficiency benefit from the dual-source and the lateral gate overlap structure of TGTFET.
Through the observation of Fig. 14a, b, it is easy to find that the Cgs of TGTFET under 1-V gate voltage is 0.15 fF/μm at Vd = 0 V and 0.7 fF/μm at Vd = 0.5 V, which is far more smaller than that of the Cgd (5.8 fF/μm at Vd = 0 V and 3.7 fF/μm at Vd = 0.5 V). Thus, the Cgg of TGTFET is mainly determined by Cgd. When Vd = 0 V, Cgg and Cgd increase rapidly with the increasing Vg, as shown in Fig. 14a. This is because with the increase of Vg, electrons are aggregated to the gate interface in the device channel, which makes the capacitance rise rapidly. When Vd = 0.5 V, Cgd does not increase obviously until Vg is increased to more than 0.6 V, as shown in Fig. 14b. This is because when Vg is low, only few lucky electrons can pass through the tunneling junction and go into the channel. Some of these lucky electrons will be participating in the recombination process, and most of the others will be rapidly collected by drain due to the 0.5-V drain voltage. Therefore, it is very difficult for these lucky electrons to stay in the device channel. However, with the Vg increase, the number of lucky electrons increases rapidly. At this moment, neither of the drain collection nor of the electron-hole recombination process can rapidly deplete these lucky electrons. Thus, the electron concentration in the channel increases and the capacitance rises rapidly. As a result, the capacitance characteristic curve tends to shift right while Vd increases, as shown in Fig. 14a, b. The above analysis and phenomena are also applicable to UTFET and LTFET, as shown in Fig. 14c–f. In addition, the gate capacitance of UTFET at 0 V and 0.5 V Vd reached 6.2 fF/μm and 5.1 fF/μm, respectively, and that of the LTFET reached 3.4 fF/μm and 2.7 fF/μm, respectively.
In this paper, a T-shape gate dual-source tunnel field-effect transistor (TGTFET) with good performance is proposed and investigated. The structure, mechanism, and the influence of device parameter on the characteristic of TGTFET are discussed. In addition, the characteristics of TGTFET, UTFET, and LTFET are discussed and compared in this paper. The dual-source regions are introduced to double the area of the tunneling junction. The gate overlap and the n+ pockets can obviously enhance the tunneling efficiency of the tunneling junction in TGTFET. Finally, the TGTFET with impressive characteristics (ION = 8.1 × 10−5 A/μm, ION/IOFF = 6.7 × 1010 and SSmin = 24.4 mV/dec) is obtained. At the same time, TGTFET is robust to DIBL, which means TGTFET can exhibit a good and stable performance in a larger applied voltage dynamic range. Furthermore, the analog/RF performance of TGTFET is studied and compared with UTFET and LTFET. The key parameter such as input/output characteristics, capacitance characteristics, GBW, and fT are analyzed. Benefiting from the no direct overlap between the gate and drain, TGTFET obtains a relatively small Cgd and Cgg. Finally, TGTFET with remarkable frequency characteristics (fT = 11.9 GHz and GBW = 2.3 GHz) is obtained. As a conclusion, it is expected that TGTFET can be one of the promising alternatives for the next generation of device in low-power and analog/RF applications.
In particular, we thank Dr. Wenxing Tian for the discussion and help in the process of writing this manuscript.
This research is supported by the National Natural Science Foundation of China (Grant Nos. 61434007 and 61504100), the Foundation for Fundamental Research of China (Grant No. JSZL2016110B003), and the Major Fundamental Research Program of Shaanxi (Grant No. 2017ZDJC-26).
SC puts forward the innovative results in this manuscript and completed the work of simulation and article writing. HL and SW supported the completion of this work and helped in the format modification and detail discussion. WL, XW, and LZ participated in the format modification and detail discussion. All authors read and approved the final manuscript.
Shupeng Chen was born in 1987. He received his B.S., M.S., and Ph.D degrees in Microelectronics from Xidian University in 2010, 2013, and 2017, respectively. He joined Xidian University in 2018. His current research interests include advanced CMOS device designs and steep-switching device designs. Hongxia Liu was born in 1968. She received her B.S., M.S., and Ph.D degrees in Microelectronics from North West University, Xi’an Jiaotong University, and Xidian University, Xi’an, China, in 1990, 1995, and 2002, respectively. She has been a professor of Microelectronics, Xidian University since 2002. Her current research interests include advanced CMOS and ultralow power device designs and reliability. Shulong Wang was born in 1983. He received his B.S. in Electronic Information Science and Technology from Xidian University in 2006 and received his M.S. and Ph.D degrees in electronic science and technology from Xidian University in 2009 and 2014, respectively. He joined Xidian University in 2014. His current research interests include advanced CMOS device designs and their applications to ultralow power integrated circuit. Wei Li was awarded a BS degree from the School of Electrical Engineering at Tianjin University of Technology, Tianjin, China, in 2014. He attended the Xidian University from 2014 to 2015. Since 2017, he has been working toward the Ph.D degree in advance at the School of Microelectronics. Xing Wang was born in 1991. He received Ph.D degree in Microelectronics from Xidian University in 2017. He joined Xidian University in 2017. His current research interests include high-k materials and advanced CMOS device designs. Lu Zhao was born in 1992. She received his B.S. degree in Microelectronics from Xidian University in 2014. She is currently working toward her Ph.D degree in Microelectronics from Xidian University. Her current research interests include high-k materials and advanced Ge-based CMOS device designs and fabrications.
The authors declare that they have no competing interests.
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- 1.Ionescu AM, Riel H (2011) Tunnel field-effect transistors as energy-efficient electronic switches. Nature. https://doi.org/10.1038/nature10679
- 2.V. Vijayvargiya and S. K. Vishvakarma. Effect of drain doping profile on double-gate tunnel field-effect transistor and its influence on device RF performance. IEEE Transactions on Nanotechnology. 2014; doi: https://doi.org/10.1109/TNANO.2014.2336812
- 3.D. Kim, Y. Lee and J. Cai et al. Low power circuit design based on heterojunction tunneling transistors (HETTs). IEEE ISLPED 2009; doi: https://doi.org/10.1109/TVLSI.2012.2213103
- 4.Hiblot G. et al. Accurate boundary condition for short-channel effect compact modeling in MOS devices. IEEE Transactions on Electron Devices 2015; doi: https://doi.org/10.1109/TED.2014.2368395
- 5.S. Bangsaruntip, G. M. Cohen, A. Majumdar et al. Universality of short-channel effects in undoped-body silicon nanowire MOSFETs. IEEE Electron Device Lett 2010; doi: https://doi.org/10.1109/LED.2010.2052231
- 6.J. Madan and R. Chaujar. Gate drain underlapped-PNIN-GAA-TFET for comprehensively upgraded analog/RF performance superlattices and microstructures 2017; doi: https://doi.org/10.1016/j.spmi.2016.12.034
- 7.G. Singh, S. I. Amin and S. Anand et al. Design of Si 0.5 Ge 0.5 based tunnel field effect transistor and its performance evaluation. Superlattices & Microstructures. 2016; doi: https://doi.org/10.1016/j.spmi.2016.02.027
- 8.Q. Huang, R. Huang and Z. Zhan et al. A novel Si tunnel FET with 36mV/dec subthreshold slope based on junction depleted-modulation through striped gate configuration. IEEE IEDM 2012; doi: https://doi.org/10.1109/IEDM.2012.6479005
- 9.U. E. Avci and I. A. Young. Heterojunction TFET scaling and resonant-TFET for steep subthreshold slope at sub-9nm gate-length. IEEE IEDM. 2013; doi: https://doi.org/10.1109/IEDM.2013.6724559
- 10.W. Y. Choi, B. G. Park and J. D. Lee et al. Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 2007; doi: https://doi.org/10.1109/LED.2007.901273
- 11.Appenzeller J., Lin Y. M., Knoch J. et al. Comparing carbon nanotube transistors - the ideal choice: a novel tunneling device design. IEEE Trans. Electron Devices. 2005; doi: https://doi.org/10.1109/TED.2005.859654
- 12.A. Villalon, G. L. Carval and S. Martinie et al. Further insights in TFET operation. IEEE Trans. Electron Devices. 2014; doi: https://doi.org/10.1109/TED.2014.2325600
- 13.V. Nagavarapu, R. Jhaveri and J. C. S. Woo. The tunnel source (PNPN) n-MOSFET: a novel high performance transistor. IEEE Trans. Electron Devices. 2008; doi: https://doi.org/10.1109/TED.2008.916711
- 14.N. Gupta, A. Makosiej and C. Anghel et al. Ultra-low-power compact TFET flip-flop design for high-performance low-voltage applications IEEE ISQED 2016; doi: https://doi.org/10.1109/ISQED.2016.7479184
- 15.N. Gupta, A. Makosiej and A. Vladimirescu et al. 3T-TFET bitcell based TFET-CMOS hybrid SRAM design for ultra-low power applications. DATE .2016; doi: https://doi.org/10.3850/9783981537079_0462
- 16.Chen S, Wang S, Liu H, et al. Symmetric U-shaped gate tunnel field-effect transistor. IEEE Transactions on Electron Devices. 2017; doi: https://doi.org/10.1109/TED.2017.2647809
- 17.Chen S, Liu H, Wang S, et al. Analog/RF performance of two tunnel FETs with symmetric structures. Superlattices & Microstructures 2017; doi: https://doi.org/10.1016/j.spmi.2017.07.013
- 18.Li W, Liu H, Wang S, et al. Reduced miller capacitance in U-shaped channel tunneling FET by introducing heterogeneous gate dielectric. IEEE Electron Device Lett 2017; doi: https://doi.org/10.1109/LED.2017.2661318
- 19.Wang Q, Wang S, Liu H et al (2017) Analog/RF performance of L- and U-shaped channel tunneling field-effect transistors and their application as digital inverters. Jpn J Appl Phys. https://doi.org/10.7567/JJAP.56.064102
- 20.D. B. Abdi and M. J. Kumar. In-built N+ pocket p-n-p-n tunnel field-effect transistor. IEEE Electron Device Lett. 2014; doi: https://doi.org/10.1109/LED.2014.2362926
- 21.W. Cao, C. J. Yao and G. F. Jiao et al. Improvement in reliability of tunneling field-effect transistor with p-n-i-n structure. IEEE Trans. Electron Devices. 2011; doi: https://doi.org/10.1109/TED.2011.2144987
- 22.A. Mallik, A. Chattopadhyay and S. Guin et al. Impact of a spacer–drain overlap on the characteristics of a silicon tunnel field-effect transistor based on vertical tunneling. IEEE Trans Electron Devices 2013; doi: https://doi.org/10.1109/TED.2013.2237776
- 23.Kim SW, Choi WY, Sun MC et al (2012) Design guideline of Si-based L-shaped tunneling field-effect transistors. Jpn J Appl Phys. https://doi.org/10.1143/JJAP.51.06FE09
- 24.S. W. Kim, J. H. Kim and T. J. K. Liu et al. Demonstration of L-shaped tunnel field-effect transistors. IEEE Trans. Electron Devices. 2016; doi: https://doi.org/10.1109/TED.2015.2472496
- 25.W. Wang, P. F. Wang and C. M. Zhang et al. Design of U-shape channel tunnel FETs with SiGe source regions. IEEE Trans. Electron Devices. 2014; doi: https://doi.org/10.1109/TED.2013.2289075
- 26.Y. Morita, T. Mori and S. Migita et al. Performance enhancement of tunnel field-effect transistors by synthetic electric field effect, IEEE Electron Device Lett. 2014; doi: https://doi.org/10.1109/LED.2014.2323337
- 27.Boucart K, Ionescu AM (2007) Length scaling of the double gate tunnel FET with a high-k gate dielectric. Solid State Electron. https://doi.org/10.1016/j.sse.2007.09.014
- 28.Narang R, Saxena M, GuptaR S, et al. Linearity and analog performance analysis of double gate tunnel FET: effect of temperature and gate stack. International Journal of VLSI Design & Communication Systems (VLSICS) 2011; doi: https://doi.org/10.1007/978-3-642-22543-7_47
- 29.Gupta S K, Baishya S. Analog and RF performance evaluation of dual metal double gate high-k stack (DMDG-HKS) MOSFETs. J Nano Electron Phys. 2013; Available: https://jnep.sumdu.edu.ua/en/component/ search/index.php?option=com_content&task=full_article&id=984
- 30.Akram M. W., B. Ghosh. Analog performance of double gate junctionless tunnel field effect transistor. Journal of Semiconductors. 2014; doi: https://doi.org/10.1088/1674-4926/35/7/074001
- 31.Mohankumar N, Syamal B, Sarkar CK (2009) Investigation of novel attributes of single halo dual-material double gate MOSFETs for analog/RF applications. Microelectron Rel. https://doi.org/10.1016/j.microrel.2009.06.006
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