Highly Flexible Multimode Digital Signal Processing Systems Using Adaptable Components and Controllers

  • Vinu Vijay Kumar
  • John Lach
Open Access
Research Article
Part of the following topical collections:
  1. Design Methods for DSP Systems


Multimode systems have emerged as an area- and power-efficient platform for implementing multiple timewise mutually exclusive digital signal processing (DSP) applications in a single hardware space. This paper presents a design methodology for integrating flexible components and controllers into primarily fixed logic multimode DSP systems, thereby increasing their overall efficiency and implementation capabilities. The components are built using a technique called small-scale reconfigurability (SSR) that provides the necessary flexibility for both intermode and intramode reconfigurabilities, without the penalties associated with general-purpose reconfigurable logic. Using this methodology, area and power consumption are reduced beyond what is provided by current multimode systems, without sacrificing performance. The results show an average of 7% reduction in datapath component area, 26% reduction in register area, 36% reduction in interconnect MUX cost, and 68% reduction in the number of controller signals, with an average 38% increase in component utilization for a set of benchmark 32-bit DSP applications.


Information Technology Power Consumption Digital Signal Processing System Quantum Information 


  1. 1.
    Chiou L-Y, Bhunia S, Roy K: Synthesis of application-specific highly-efficient multi-mode systems for low-power applications. Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE '03), March 2003, Munich, Germany 96-101.Google Scholar
  2. 2.
    van der Werf A, Peek MJH, Aarts EHL, Van Meerbergen JL, Lippens PER, Verhaegh WFJ: Area optimization of multi-functional processing units. Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD '92), November 1992, Santa Clara, Calif, USA 292-299.Google Scholar
  3. 3.
    Vijay Kumar V, Lach J: Designing, scheduling, and allocating flexible arithmetic components. Proceedings of 13th International Conference on Field Programmable Logic and Applications (FPL '03), September 2003, Lisbon, Portugal 1166-1169.Google Scholar
  4. 4.
    Vijay Kumar V, Lach J: Heterogeneous redundancy for fault and defect tolerance with complexity independent area overhead. Proceedings of 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '03), November 2003, Boston, Mass, USA 571-578.CrossRefGoogle Scholar
  5. 5.
    Chiricescu SMSA, Schuette MA, Glinton R, Schmit H: Morphable multipliers. Proceedings of 12th International Conference on Field Programmable Logic and Applications (FLP '02), September 2002, Montpellier, France 647-656.Google Scholar
  6. 6.
    Compton K, Hauck S: Flexibility measurement of domain-specific reconfigurable hardware. Proceedings of ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays (FPGA '04), February 2004, Monterey, Calif, USA 155-161.Google Scholar
  7. 7.
    Kim K, Karri R, Potkonjak M: Synthesis of application specific programmable processors. Proceedings of ACM/IEEE 34th Design Automation Conference (DAC '97), June 1997, Anaheim, Calif, USA 353-358.Google Scholar
  8. 8.
    Guerra LM, Potkonjak M, Rabaey JM: Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1998, 6(1):158-167.CrossRefGoogle Scholar
  9. 9.
    Bozorgzadeh E, Memik SO, Kastner R, Sarrafzadeh M: Pattern selection: customized block allocation for domain-specific programmable systems. Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '02), June 2002, Las Vegas, Nev, USAGoogle Scholar
  10. 10.
    Even G, Mueller SM, Seidel P-M: A dual mode IEEE multiplier. Proceedings of 2nd Annual IEEE International Conference on Innovative Systems in Silicon (ISIS '97), October 1997, Austin, Tex, USA 282-289.Google Scholar
  11. 11.
    Paulin PG, Knight JP: Force-directed scheduling for the behavioral synthesis of ASIC's. IEEE Transactions on Computer-Aided design of Integrated Circuits and Systems 1989, 8(6):661-679. 10.1109/43.31522CrossRefGoogle Scholar
  12. 12.
    Park S, Choi K: Performance-driven high-level synthesis with bit-level chaining and clock selection. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2001, 20(2):199-212. 10.1109/43.908436MathSciNetCrossRefGoogle Scholar
  13. 13.
    Haralick RM, Shapiro LG: Computer and Robot Vision. Addison-Wesley, Reading, Mass, USA; 1992.Google Scholar
  14. 14.
    Högstedt K, Orailoglu A: Integrating binding constraints in the synthesis of area-efficient self-recovering microarchitectures. Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD '94), October 1994, Cambridge, Mass, USA 331-334.Google Scholar
  15. 15.
    Mallon DJ, Denyer PB: A new approach to pipeline optimisation. Proceedings of European Design Automation Conference (EDAC '90), March 1990, Glasgow, Scotland, UK 83-88.Google Scholar
  16. 16.
    Karri R, Orailoglu A: High-level synthesis of fault-secure microarchitectures. Proceedings of 30th ACM/IEEE International Conference on Design Automation (DAC '93), June 1993, Dallas, Tex, USA 429-433.CrossRefGoogle Scholar

Copyright information

© Kumar and Lach 2006

Authors and Affiliations

  • Vinu Vijay Kumar
    • 1
  • John Lach
    • 1
  1. 1.Brown Department of Electrical and Computer EngineeringUniversity of VirginiaCharlottesvilleUSA

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